Sorry for being off-topic but ...

especially with FPGAs were you can't just stick a scope probe on an internal signal.
I don't know about Xilinx, but Altera has SignalTap II which allows you to do just that! It's quite nice, although it uses the on-chip ram to buffer values, so it can be ...

Hey, just wanted to pop in here and let you know this is an awesome project!

I work in Verilog all day long for my job :P I've always wanted to dig into building out actual hardware around an FPGA, but just haven't had the time or money to learn it all up.

So, it's cool to see your project with a ...

Update 2 - Now with less bugs!

I've now modified the starfield code to wait until every 8th frame before updating, thus slowing it down to a more visible speed :P I also fixed the bug in my framebuffer->DVI module and so now everything displays as it should.

YouTube video

My next work will be ...

I should also point out that the chip, as is, can be single stepped, and all the internal registers and control signals can be dumped. :D Really, this is for my own good, since I need to debug the countless mistakes I made. Still, I find it cool to be able to run a replica of the 6502 and peek in on ...

Update 1 - Now runs on Cyclone 4 FPGA!

Well, I fixed a few bugs in the 6502 core that cropped up while running the visual6502 example. Then I copied over the starfield example from 6502asm.com and worked on getting that to run correctly. After re-doing the tcstate logic, a few random control ...

This is a continuation of the topic that started here.

6502 Verilog Replica
by Xor

Summary
A logically accurate replica of the NMOS 6502, written in Verilog HDL, and based on the transistor netlist available from Visual6502.org .

Goal
The main goal of the project is for my own personal ...

YAY! It looks like I've gotten the full visual6502 example program running! There are still 27 control signals left unimplemented; they aren't exercised by the simple example program. Nevertheless, I'm happy to have something running.

I guess the next step is to find examples on 6502asm.com that ...

I couldn't find a colorized version of the 6502 Block Diagram. I found it difficult to follow where things like DB and SB go, because they criss-cross with ADL, ADH, and blend in with other lines and blocks. So, I created my own colorized version. I am a tech guy, not an artist, so you'll have to ...

Looks like I finally got JSR Abs working. It seems to be more or less correct (ADL is incorrect for one cycle, but doesn't effect anything; possibly other things like that).

http://forum.6502.org/images/migrated/013258-000.jpg

2 instructions down, 7 more to go before the visual6502 demo works ...

On the subject of latches and clocking, here's a thing: when the 6502 fetches a second operand byte which appears on the high address byte in the very next phase, you'll find that there's a phi2 latch to capture the databus into the IDL, and then in phi1 the data actually has to pass through 2 phi1 ...

Quick progress update. I got LDA # (opcode A9) working, and am putting in all the logic needed for JSR Abs.

JSR Abs is both fun and irritating. It's enlightening to see how they conserved resources by shuffling data all around the chip, but it also means I have to implement a large number of ...

Arlet: To be honest, I would much prefer to have done a single clock implementation from the beginning :P My job affords me the luxury of working with single clock systems all the time, with only the occasional need to cross clock domains (which I despise doing and debugging). But building this ...

Arlet, yeah, the clocking is a little weird. I updated the clocking code to more closely model how the 6502 generates its clock. From what I remember in the documentation it pushes the edges of the two clocks away from each other; far enough that it satisfies setup and hold times.
When I synthesize ...

Thank you for the encouragement, BigEd.

After putting in the PLA, IR fetching logic, and fixing a few mistakes, I got it to work:

http://forum.6502.org/images/migrated/013241-000.jpg

For now, the test module manually feeds the correct data to the external databus. I'll need to add the logic for ...

PHEW! It looks like I finally have enough logic built up to get something working. I just need to plug in a partial PLA and it should correctly fetch instructions and run the timing control:

module 6502(clk, bi_data);

input clk;
inout [7:0] bi_data;

reg [7:0] pd = 8'd0;
reg clock1, clock2 ...