Update 1 -
Now runs on Cyclone 4 FPGA!
Well, I fixed a few bugs in the 6502 core that cropped up while running the visual6502 example. Then I copied over the starfield example from
6502asm.com and worked on getting that to run correctly. After re-doing the tcstate logic, a few random control logic fixes, and putting in the code for a few more control lines, I was able to get the starfield code running.
Having done all that, I added a video output module, proper dual-clock generation, debugging sources and probes, and got the whole thing to synthesize for my Cyclone 4 FPGA.
And then, of course, I had plenty of bugs to fix. But now I have something half-way decent on the screen:
http://www.youtube.com/watch?v=b7O7QJsaHHk
I modified the starfield example to include a VSYNC wait loop, because with a 1MHz clock it ran too fast and obviously caused tearing. I'll probably need to add a small loop that waits for a few VSYNCS, instead of just one, because, as you can see in the video, it still runs too fast.
There's still a bug or two left, but I'm happy to have something running.
I'll get around to putting the code up somewhere (github?) so any interested parties can laugh at it. Some of the code is well written and accurate to the 6502 ... other parts ... not so pretty
![Razz :P](./images/smilies/icon_razz.gif)