Hi Drass, I suppose both approaches have pros and cons. Yours is cleaner and more to the point, and I think it's the way logisim is supposed to be used. I suspect I abused logisim by attempting to make a schematic with it, but it's not designed to be a schematics tool. I think I decided to do so ...

Btw, I don’t quite get how you perform the sbc function in the model. That should require the negation of one of the ALU inputs and I was curious about how that would add to the FET adder propagation delay. I’ve been looking for XOR gates at one of the ALU inputs but I can’t see them. Please can you ...

but you do need to keep the 7400 series ICs in mind as well. In this case I’ve marked various Logisim components with the 7400 series equivalents I intend to use. I’m also careful to reflect the correct pinouts. For example, I put inverters in front of inputs which I know are active-low on the 7400 ...

Hi Drass,

For those that do have Logisim, I am using Logisim "Evolution". When you load the C74-100 circuit file, you will be greeted by the following: It looks very professionaly done and works very well.

Maybe it needs to be clarified that this is intended to run on Kevin Wash "Logisim ...

Hi Drass,

I'm unsure if you have already mentioned this in the past, but I am curious about what are you using for your instruction decoder. It looks to me that the typical ROMs are totally out of specs for your speed requirements, so what are you using instead?

(It would also be great if at some ...

Hi Drass, congratulations for that, and for the short time in which you achieved it !

Hi Drass, thanks for that. It makes a lot of sense. I'm essentially doing the same with my CPU74 logisim model. My "text" microinstructions are actually defined as expressions in my software simulator. From that, I manually create a table in a text file with the the control signals for each ...

Hi Drass, I'm curious if you use your text notation for microinstructions only as a reference document of the actual control signals required, or whether you have created some sort of software utility to convert them to the actual contents of the decode ROM(s). (not sure if the later would be really ...

Hi Drass,

The first microinstruction loads the inputs of the ALU and the second performs the ALU operation itself. To be clear, the RISC form of the instruction would execute the same sequence of steps with respect to the ALU as it works down the pipeline. But it remains an atomic unit that ...

Hi Dieter,

Joan, you happen to have some schematics at hand ?

The relay computer engineers probably didn't have to worry much about capacitances. :) The only public documentation that I am aware of, is from the Konrad Zuse Internet Archive. But last time I checked, the link was broken http://zuse ...

Or we could say it's an old dimension, because the relay computer engineers or the past designed their ALUs on the consideration of asymmetrical behaviour of mechanical relays

On the face of it, computing Z should be no worse than a carry-chain problem, and indeed the inputs to the Z function arrive earliest from the LSB and latest from the MSB, so Z might only need to be a gate-delay behind C. (I say this, knowing that computing Z often does seem to be a time-consuming ...

I suspect even in more sophisticated ALUs, the LSB results come sooner. So it might be an advantage to structure the Z logic to take that into account, with the MSB bits having a shallower logic depth.

(Not just logic depth: sometimes a many-input logic gate will in practice react faster to some ...

Hi Ed,

On the face of it, computing Z should be no worse than a carry-chain problem, and indeed the inputs to the Z function arrive earliest from the LSB and latest from the MSB, so Z might only need to be a gate-delay behind C. (I say this, knowing that computing Z often does seem to be a time ...

Now this gives me quite a headache.

Drass, since the ALU input latches will be edge triggered 74AUC16374 chips or such...
have you considered building the registers with transparent latches like 74AUC16373 ?

When using transparent latches for the registers (transparent during PHI2=HIGH),
the ...