akohlbecker wrote:
suggestions on how to fix my signal integrity problems on the current build
It's best to avoid thinking of the Power & Ground Distribution network as something for connecting the chips to the power supply. Where high frequencies are concerned,
its real job is to connect the chips to one another.
Imagine Chip A in Location A. We know it outputs a signal whose current gets carried by a conductor to Chip B, some distance away. It's easy to forget that, in order to complete the circuit, a
return current must flow through the Power & Ground Distribution network from Chip B back to Chip A.
The return current will follow the path of least
inductance (the resistance is low enough not to matter). Inductance is the enemy, and we can minimize inductance by providing a return path that's
in close proximity to the signal path. This is crucial. The signal current and return current flow in opposite directions, and
when two opposing currents are in close proximity their magnetic fields tend to mutually cancel. And that's what we want, because it reduces inductance.
(BTW there's another way of discussing this effect. Sometimes in reference documents the signal and return path are described as forming a
loop, with the goal being to reduce the
loop area -- and thus the number of lines of magnetic flux contained by the loop. Closer proximity means less loop area. In turn we get fewer lines of magnetic flux passing through the loop, which results in less inductance.)
The Power & Ground Distribution Network can support this by making many paths available. For every signal wire connecting Chip A to Chip B there would ideally also be, in close proximity to the signal wire, power and ground wires connecting Chip A and Chip B. This isn't practical on a wireless breadboard (or a 2-layer PCB), but you can achieve some of the same benefit by forming the Power & Ground Distribution network into a coarse grid (a fine grid is even better). Remember: the goal is that, for any signal from one chip to another, you want the return current to be able to follow much the same path, in close proximity, back to the first chip.
In the first diagram below I've highlighted your Power & Ground Distribution network, and we can see that, as a grid, it has many serious gaps. If this were the roadmap of a city we'd say it has far too many cul de sacs, making driving a nightmare. The second diagram shows some possible connections you could add to provide relief to the frustrated drivers!
Attachment:
'as is'.png [ 661.41 KiB | Viewed 3972 times ]
Attachment:
improved grid.png [ 425.67 KiB | Viewed 3972 times ]
And, here's another diagram suggesting a further improvement. Since you have several bundles of conductors in midair, vertically separated from the grid, you would do well to add at least a ground wire in close proximity to each of those bundles. Because the goal is to conduct current, both end points (not just one) need to attach to the local ground. (And if there are three or more end points,
all should ideally be grounded.)
Attachment:
specific return paths.png [ 423.93 KiB | Viewed 3972 times ]
Hope this helps. I think we could also improve the way your bypass capacitors are arranged, but that's a topic for another post.
The WDC '816 is always challenge, due to the very fast transitions on its outputs. And with a breadboard project of this size you may only find it possible to reduce the number of glitches, rather than eliminating them entirely.
BTW you may also want to see my recent post
here, also on the subject of Power & Ground Distribution grids.
-- Jeff
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