joanlluch wrote:
I think this only works (possibly) because the 6502 uses two cycles anyway to complete instructions. So in fact you have a two step gap between the fetch-decode-execute-writeback sequence of one cycle to the next. Or in other words, the next instruction fetch happens while the current cycle is in the executing stage, not while it is in the decode stage, as it would be the case for a standard pipelined risc processor. Is this right, or I am missing something fundamental here?
The pipeline always fetches and executes one microinstruction per cycle. We avoid WRITEBACK data hazards by ensuring that there is an intervening microinstruction between a register read in the DECODE stage and a corresponding register write in the WRITEBACK stage. On a 6502 multi-cycle implementation, a register write operation is always followed by an operand-fetch for the next instruction (or a nop if the next instruction is a single-byte instruction). Hence, data hazards never occur.
In a RISC implementation, it might be useful to think of this intervening microinstruction as a “data delay slot” which can be “filled” to avoid a stall. You can dispense with hardware hazard checks by having the compiler (or some other mechanism) fill these slots ahead of time, either with other instructions in the program, or with nops that resolve the data hazard but do not preform any useful work.
