I normally use 0.6 mm (23,6 mil) via size with 0.25 mm (9.8 mil) finished holes. That's the smallest I can get from eurocircuits for their standard process. There's always the option of going smaller, for additional cost. Start out by looking at board houses, and see what options they have. I usually run a VCC plane anyway, so that all left over space can be used. That's less work than running traces. Just make sure you don't cut off anything.

Edit: if you're hand soldering, you could put a via inside an SOIC pad to save space. This is not recommended for reflow soldering, because the via will wick away the solder.

Via in the signal paths (0.006 inch traces) are 0.026 inch diameter with 0.008 inch holes. Other via sizes depend on the traces to which they connect.

Incidentally, that board is a four-layer design, with the inner layers being Vcc and ground.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Thanks Gents. Just checked with OSH Park. They support 10 mil drill (+/- 2.5mil) with a 4 mil "annular ring" as standard for a 4 layer board. That suggests I could end up with 18 mil total diameter of copper and a 12.5mil hole in the middle of it. Nice and small but it doesn't leave a lot of copper around the hole - just hope they can hit the center accurately Makes perfect sense. I'll run traces and then just fill in the plane once it's all done.
That's a great idea! I checked with the board house just to make sure and it's not a problem for them. By the way, Eagle CAD generates an error when you do this unless: (1) the via has the same name as the signal, and (2) the Design Rule for the distance between a pad and a via of the same name is set to zero. Took me a while to figure that out.
Thanks Garth. I chose 24 mil rather arbitrarily. Out of interest, I took a look at this Trace Width Calculator. It suggests even fairly narrow traces will do wrt temperature rise. I had just assumed VCC lines needed to be quite wide even with bypass caps - evidently not! Nice! I'm in for quite a lot of SMD soldering on this project so this is very reassuring

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C74-6502 Website: https://c74project.com

Before my left eye went south on me, I could easily solder SMT parts with pins on 50 mil centers. POC V1.1 has the SRAM in an SOJ32 package and a MAX-238 in an SOIC24 package. I used some liquid flux to make the pads a bit tacky, which helped to keep the part in place. Using tweezers to position and press down on the part, I heated diagonally opposite pins until the reflow melted and bonded to the pins. With the package now secured, I thoroughly cleaned and tinned the soldering iron tip and then used a drag technique to solder the rest of the pins. The SOIC24 was the easier of the two to solder, since the pins extend outward from the package. Judicious use of desoldering braid cleaned up any little boo-boos.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

I have soldered the occasional SD card socket, but that's about it as far as SMD is concerned. To get more practice I've ordered a couple of those 1-dollar DIY kits from ebay, just a silly thing with blinkenlights, but they have several surface mount chips. Can as well make something that does something while practicing.

Be careful with the flux though. I once used some flux pens, and the flux got under TQFP packages, and started to corrode the vias.

Submerge and lightly rock and scrub the final result in alcohol for a few minutes. That's what I always do. Should remove all the flux, even under chips. (Of course, use good judgement about what parts will tolerate this treatment (e.g. switches might not). ICs, SMD Rs and Cs, and non-delicate connectors (like IC sockets and IDC headers) should all be okay).

Was that a RHOS PCB where that happened? I've heard of corrosion occurring on those PCBs just because of the environment in which the board is being used.

I have modules built on non-RHOS boards that have been in use for many years, some in cabinets that are outdoors and thus are occasionally exposed to high humidity. I've never seen any evidence of via or pad corrosion. It could be that is because the reflow is lead/tin.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Yes, I think it was post-RHOS time.

Is the "drag" technique the preferred method even for SOIC packages? It looks like magic on the videos I've seen. I'm instinctively more comfortable with a pin-by-pin approach, but that's probably because I've only soldered DIP packages before (and only very few of them at that). BDD, did you use a chisel-tip iron or one of those hollow tips? I was assuming that because Garth mentioned not using extra flux and a chisel-tip it was pin-by-pin in that instance.

Thanks for all the suggestions - I really would like these boards to have that pristine look

Incidentally, Card B is coming along, but I have a ways to go yet. I'm encouraged that it just might work in 4 layers after all - using 6 mil traces, 5 mil spacing and 18 mil vias. Being VERY careful about how horizontal traces are used seems to be the key to this board - at least the bottom section (horizontal traces are in dark blue, air-wires in bright yellow). I'm working my way up from the bottom so I'd say I'm about 1/5th of the way

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C74-6502 Website: https://c74project.com

I got the hang of it by studying this video. The narrator describes the use of the drag technique on several packages, which worked fine for me.


Be sure to run a design rule check on the layout. You may find that 5 mil spacing won't pass the DRC.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

I describe how I did it, at viewtopic.php?f=4&t=4329&p=48875#p48875 . I intentionally bridge the entire side; so it's even worse than you thought! (I can joke about it because the results speak for themselves.) I don't use a magnifier of any kind either, but my up-close vision is excellent.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Thanks for the pointers and video on SMD soldering - great to have this reference.

Regarding DRC, I've been checking the board as I go and all seems well so far. It's definitely a tight squeeze, but it feels like I'm getting through it. I'm not having to use the VCC layer nearly as much as expected and Arlet's suggestion of putting via's right on the pads has let me get out of a bind a few times . Nearly half way there now ...

Cheers!

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C74-6502 Website: https://c74project.com

Another milestone along the journey ... the ALU & CU Card is now routed

It took some effort to squeeze things in (and the suggestions above proved essential!). In the end, I'm very happy with the result - over 100 ICs, as many bypass caps, ROM sockets, connectors and assorted passives, along with VCC and GND planes, and even one Canadian flag . Here is a pic of the top and bottom traces along with the top silkscreen:
As expected, I had to put traces on the VCC layer, but not nearly as many as I feared:
Surprising really how much room there is, and I'm glad I didn't have to resort to a larger board. I quite like the dimensions currently (not to mention that my copy of Eagle CAD won't let me go any bigger - I did notice, btw, that Altium has a new free version of it's software with no such limit, very interesting).

Ok. Next up is more checking and double-checking, and then finally getting ready to order some parts

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C74-6502 Website: https://c74project.com

You should put a graphic of a bull moose next to the maple leaf, since this thing sounds as though it will be as big as Bullwinkle. With that many ICs in the circuit, the lights in your neighborhood might dim when you turn on the power.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!