SBC Blaufuchs-II

[8BIT]

norby wrote:

Is the ENC28J60 any good?

The only problem I've had with the ENC28J60 module is sometimes it does not start up. I have to re-initialize it or even power cycle it for it to start. Once running, it runs very well. That issue may be caused by me and not the module, I just haven't had it happen frequently enough to drive me to investigate it.

Daryl

[norby]

BigDumbDinosaur wrote:

The +/- 12 volt outputs are mandatory in the ATX2.0 and ATX-EPS standards, so they will be around for a long time. Also, power supplies have to be backward compatible with older hardware to assure interchangeability.

You are right I was confusing it with the -5V that is no longer mandatory.

BigDumbDinosaur wrote:

Anyhow, to use /KS (push button input) and /DPWR to control the power supply, proceed as follows:

1. Create a voltage divider consisting of a 2.2K resistor in series with a 3.3K resistor.
2. Connect the free end of the 2.2K resistor to +5VSB on your power supply's main motherboard connector—that would be pin 9.
3. Connect the free end of the 3.3K resistor to ground.
4. Attach the junction of these resistors to Vbaux on the DS1511.
5. Connect /KS through a 3.3K resistor to Vbaux.
6. Connect /DPWR to PS_ON# on your power supply's main connector—either pin 14 (20 pin connector) or pin 16 (24 pin connector).
7. Connect one side of a push button to /KS. Connect the other side of the push button to ground.

After reading the DS1511 datasheet I get the impression that VBAUX can actually handle +5V.
Page 2 "Recommended DC operating conditions"
Auxiliary Battery Voltage (note 3) VBaux
Says 5.3 V max.

Later in the text they talk about 2.5V - 3.7V for VBAUX but I guess that applies to the 3.3V (W) version.

I just breadboarded the circuit you described, with and without a voltage divider and both seems to work perfectly.
The only gotcha is that pushing /KS again will not automatically power off the system. It seems that it can be handled in
software though.

BigDumbDinosaur wrote:

As for the DS1511's /RST output, it doesn't respond to a push button the way the DS1813 does, so I question its value to you in this design. If you decide to use /RST, under what circumstances would you assert it? If you arrange for the watchdog to assert it, what about using the watchdog for jiffy IRQ generation? You can't do both.

After reading the datasheet I got the impression that the watchdog and irq where unrelated, I guess I was wrong, I changed my schematic - /RST tied to VCC via a resistor.

BigDumbDinosaur wrote:

In lieu of tri-stating the RDY output on the CPLD, you can isolate the circuit with a low-power Schottky diode, with the anode connected to the RDY pin on the '816. A pullup resistor is required no matter how you do it. Better to directly connect RDY to the CPLD and tri-state when inactive. That way you can use the CPLD to detect when a WAI is being executed.

Noted, I have removed the RDY_OUT.

/norby

[norby]

GARTHWILSON wrote:

Were those really weak? BDD was talking about some kind that was really thin. These however are the same thickness as the pins that the ribbon cable on IDE hard-disc drives plug into on a PC motherboard, much thicker than IC pins. The only thing you have to be careful of is that when you pull a module out of the socket, you pull it out straight so you don't bend the pins on one end. It would be possible to put the socket on the module and the pins on the motherboard (instead of vice-versa), although I'll have to figure out a way to test it-- maybe just solder a couple of pin headers tail to tail.

Weak and on the Amigas they had a tendency to wiggle their way out of the sockets, due to heat cycles I guess.
When the machine started beheaving erratic, reseating / pushing it back in usually helped

/norby

[BigDumbDinosaur]

norby wrote:

After reading the DS1511 datasheet I get the impression that VBAUX can actually handle +5V.
Page 2 "Recommended DC operating conditions"
Auxiliary Battery Voltage (note 3) VBaux
Says 5.3 V max.

Later in the text they talk about 2.5V - 3.7V for VBAUX but I guess that applies to the 3.3V (W) version.

As I said, Dallas' data sheets can be confusing. Whomever was responsible for their technical writing needed to be reassigned to janitorial service.

Several years ago, I talked to Maxim's tech support on this subject and was told that Vbaux was intended to be powered by a CR2032 battery or similar. I tried to pin the guy down on whether Vbaux could be directly powered off the +5VSB output of an ATX power supply, but all he would say was it was intended to be powered by a 3.3 volt battery. So I decided that he was trying to tell me that the 5.3 volt max was probably a "do not exceed" value and that Vbaux really should be powered by 3.3 volts. Hence the voltage divider.

Quote:

I just breadboarded the circuit you described, with and without a voltage divider and both seems to work perfectly. The only gotcha is that pushing /KS again will not automatically power off the system. It seems that it can be handled in software though.

There's a defined sequence to follow in order to power down under software control. You will need to peruse the data sheet for the details, starting on page 17. Look at the PAB bit in register $0E.

It's also possible to detect closure of the power push button while the system is powered, and in fact, you can arrange for that closure to generate an IRQ. In such a case, the IRQ could cause the operating system kernel to initiate an orderly system shutdown when the power push button is pressed, like what happens with Linux or Window$.

Quote:

After reading the datasheet I got the impression that the watchdog and irq where unrelated, I guess I was wrong, I changed my schematic - /RST tied to VCC via a resistor.

The DS1511 can be programmed so that an underflow of the watchdog will either generate an IRQ or toggle /RST. In my application, I have the watchdog timing out at 10ms intervals, but automatically reloading and continuing. Hence it isn't necessary to restart the timer each time it underflows and interrupts.

See following code for a set of definitions for the DS1511 and the 26C92.

Code: Select all

;================================================================================
;
;DALLAS DS1511 REAL-TIME CLOCK DEFINITIONS
;
nr_rtc   =32                   ;total registers ($14-$1F reserved)
;
;
;	register offsets...
;
wr_sect  =$00                  ;TOD seconds ($00-$59 BCD)
wr_mint  =$01                  ;TOD minutes ($00-$59 BCD)
wr_hrst  =$02                  ;TOD hour ($00-$23 BCD)
wr_dowt  =$03                  ;day of week ($01-$07 BCD)
wr_datt  =$04                  ;date ($01-$31 BCD)
wr_mon   =$05                  ;month & control...
;
;	xxxxxxxx
;	||||||||
;	|||+++++———> month ($01-$12 BCD)
;	||+————————> 1: enable 32 Khz at SQW when on battery
;	|+—————————> 0: enable 32 KHz at SQW when on Vcc
;	+——————————> 0: enable oscillator
;
wr_yrlo  =$06                  ;year LSB ($00-$99 BCD)
wr_yrhi  =$07                  ;year MSB ($00-$39 BCD)
wr_seca  =$08                  ;alarm seconds & IRQ control...
;
;	xxxxxxxx
;	||||||||
;	|+++++++———> alarm seconds ($00-$59 BCD)
;	+——————————> 1: IRQ once per second
;
wr_mina  =$09                  ;alarm minutes & IRQ control...
;
;	xxxxxxxx
;	||||||||
;	|+++++++———> alarm minutes ($00-$59 BCD)
;	+——————————> 1: IRQ when TOD secs = alarm secs
;
wr_hrsa  =$0a                  ;alarm hour & IRQ control...
;
;	x0xxxxxx
;	| ||||||
;	| ++++++———> alarm hour ($00-$23 BCD)
;	+——————————> 1: IRQ when TOD secs & mins = alarm secs & mins
;
wr_dowa  =$0b                  ;alarm date/day & IRQ control...
;
;	xxxxxxxx
;	||||||||
;	||++++++———> alarm day ($01-$07 BCD) or date ($01-$31 BCD)
;	|+—————————> 0: alarm date set
;	|            1: alarm day set
;	+——————————> 0: IRQ when TOD & day/date = alarm TOD & day/date
;	             1: IRQ when TOD = alarm time
;
wr_wdms  =$0c                  ;watchdog millisecs*10 ($00-$99 BCD)
wr_wds   =$0d                  ;watchdog seconds ($00-$99 BCD)
wr_cra   =$0e                  ;control register A...
;
;	xxxxxxxx
;	||||||||
;	|||||||+———> 1: IRQ pending (read only)
;	||||||+————> 1: IRQ = watchdog timer
;	|||||+—————> 1: IRQ = kickstart (read only)
;	||||+——————> 1: IRQ = TOD alarm
;	|||+———————> 0: PWR pin = active low
;	|||          1: PWR pin = high-Z
;	||+————————> 0: PWR pin = high-Z wo/Vcc present
;	||           1: PWR pin = active low wo/Vcc present
;	|+—————————> 1: aux external battery low (read only)
;	+——————————> 1: external battery low (read only)
;
wr_crb   =$0f                  ;control register B...
;
;	x0xxxxxx
;	| ||||||
;	| |||||+———> 0: watchdog generates IRQ
;	| |||||      1: watchdog generates reset
;	| ||||+————> 1: watchdog IRQ/reset enabled
;	| |||+—————> 1: kickstart IRQ enabled
;	| ||+——————> 1: TOD alarm IRQ enabled
;	| |+———————> 1: TOD alarm wakeup enabled
;	| +————————> 1: NVRAM address autoincrement enabled
;	+——————————> 0: TOD & date register update disabled
;	             1: TOD & date register update enabled
;
wr_nvra  =$10                  ;NVRAM address port ($00-$FF)
wr_rsva  =$11                  ;reserved
wr_rsvb  =$12                  ;reserved
wr_nvrd  =$13                  ;NVRAM data port
;
;================================================================================
;
;NXP26C92 DUAL ACIA DEFINITIONS
;
nc_c92a  =2                    ;number of channels
nr_c92a  =8                    ;registers per channel
nr_26c92 =nr_c92a*nc_c92a      ;total registers
;
;
;	register offsets...
;
dr_mra   =%0000                ;ch A mode select...
;
;	xxxx0xxx ——> mode 0 settings
;	|||| |||
;	|||| +++———> baud rate extend:  000: normal
;	||||                            001: extended mode 1
;	||||                            100: extended mode 2
;	||++———————> TxD FIFO IRQ level: 00: 8
;	||                               01: 4
;	||                               10: 6
;	||                               11: 1
;	|+—————————> RxD FIFO IRQ level:  0: 1-5: see also MR1:6
;	|                                 1: 6-8: see also MR1:6
;	+——————————> RxD watchdog:        0: disable
;	                                  1: enable
;
;	xxxxxxxx ——> MR1 settings
;	||||||||
;	||||||++———> data format:  00: 5 bit
;	||||||                     01: 6 bit
;	||||||                     10: 7 bit
;	||||||                     11: 8 bit*
;	|||||+—————> parity type:   0: even*
;	|||||                       1: odd
;	|||++——————> parity mode:  00: check
;	|||                        01: force
;	|||                        10: don't check*
;	|||                        11: multidrop
;	||+————————> error mode:    0: character*
;	||                          1: block
;	|+—————————> RxD IRQ mode:  0: RxD ready*
;	|                           1: FIFO full
;	+——————————> RxD RTS mode:  0: off
;	                            1: on*
;	* = default setting
;
;	xxxxxxxx ——> mode 2 settings
;	||||||||
;	||||++++———> stop bit length
;	||||
;	|||+———————> TxD CTS mode:        0: off
;	|||                               1: on
;	||+————————> TxD RTS mode:        0: off
;	||                                1: on
;	++—————————> channel mode:       00: normal
;	                                 01: auto echo 
;	                                 10: local loop
;	                                 11: remote loop
;
dr_sra   =%0001                ;ch A status (R)...
;
;	xxxxxxxx
;	||||||||
;	|||||||+———> 1: RxD FIFO not empty
;	||||||+————> 1: RxD FIFO full
;	|||||+—————> 1: TxD FIFO not empty
;	||||+——————> 1: TxD FIFO empty
;	|||+———————> 1: RxD overrun
;	||+————————> 1: parity error
;	|+—————————> 1: framing error
;	+——————————> 1: break received
;
dr_csra  =dr_sra               ;ch A clock select (W)...
;
;	xxxxxxxx
;	||||||||
;	||||++++———> TxD baud rate & BRG source
;	++++———————> RxD baud rate & BRG source
;
dr_cra   =%0010                ;ch A command (W)...
;
;	xxxxxxxx
;	||||||||
;	||||||++———>   00: no operation
;	||||||         01: enable receiver
;	||||||         10: disable receiver
;	||||||         11: illegal operation
;	||||++—————>   00: no operation
;	||||           01: enable transmitter
;	||||           10: disable transmitter
;	||||           11: illegal operation
;	++++———————> 0000: no operation
;	             0001: select MR1
;	             0010: reset & disable receiver
;	             0011: reset & disable transmitter
;	             0100: reset error status
;	             0101: reset break IRQ
;	             0110: start TxD break
;	             0111: stop TxD break
;	             1000: assert RTS
;	             1001: deassert RTS
;	             1010: enable C/T timeout mode
;	             1011: select MR0
;	             1100: disable C/T timeout mode
;	             1101: undefined
;	             1110: standby power mode
;	             1111: normal power mode
;
dr_rhra  =%0011                  ;ch A RxD FIFO (R)
dr_thra  =dr_rhra                ;ch A TxD FIFO (W)
dr_ipcr  =%0100                  ;input port change (R)
dr_acr   =dr_ipcr                ;auxiliary control register (W)...
;
;	xxxxxxxx
;	||||||||
;	|||||||+———> 1: enable IP0 IRQ
;	||||||+————> 1: enable IP1 IRQ
;	|||||+—————> 1: enable IP2 IRQ
;	||||+——————> 1: enable IP3 IRQ
;	|+++———————> C/T setup:
;	|
;	|            654  Mode     Source
;	|            ———————————————————————————————
;	|            000  counter  IP2
;	|            001  counter  TxD Ch 1 1X clock
;	|            010  counter  TxD Ch 2 1X clock
;	|            011  counter  Xtal/16
;	|            100  timer    IP2
;	|            101  timer    IP2/16
;	|            110  timer    Xtal
;	|            111  timer    Xtal/16
;	|            ———————————————————————————————
;	|
;	+——————————> 0: select BRG set #1 (38.4k max)
;	             1: select BRG set #2 (19.2k max)
;
dr_imr   =%0101                ;interrupt enable mask (W)...
;
;	xxxxxxxx
;	||||||||
;	|||||||+———> 1: enable ch A THR ready
;	||||||+————> 1: enable ch A RHR ready/FIFO full
;	|||||+—————> 1: enable ch A change in break
;	||||+——————> 1: enable C/T ready
;	|||+———————> 1: enable ch B THR ready
;	||+————————> 1: enable ch B RHR ready/FIFO full
;	|+—————————> 1: enable ch B change in break
;	+——————————> 1: enable IP0-IP3 state change
;
dr_isr   =dr_imr               ;interrupt status (R)...
;
;	xxxxxxxx
;	||||||||
;	|||||||+———> 1: ch A THR ready
;	||||||+————> 1: ch A RHR ready/FIFO full
;	|||||+—————> 1: ch A change in break
;	||||+——————> 1: C/T ready
;	|||+———————> 1: ch B THR ready
;	||+————————> 1: ch B RHR ready/FIFO full
;	|+—————————> 1: ch B change in break
;	+——————————> 1: IP0-IP3 state change
;
dr_crur  =%0110                ;C/T MSB preset (W)
dr_crlr  =%0111                ;C/T LSB preset (W)
dr_ctu   =dr_crur              ;C/T MSB value (R)
dr_ctl   =dr_crlr              ;C/T LSB value (R)
dr_mrb   =%1000                ;ch B mode select...
;
;	xxxx0000 ——> MR0 settings
;	||||
;	||++———————> TxD FIFO IRQ level: 00: 8
;	||                               01: 4
;	||                               10: 6
;	||                               11: 1
;	|+—————————> RxD FIFO IRQ level:  0: 1-5: see also MR1:6
;	|                                 1: 6-8: see also MR1:6
;	+——————————> RxD watchdog:        0: disable
;
;	xxxxxxxx ——> MR1 settings
;	||||||||
;	||||||++———> data format:  00: 5 bit
;	||||||                     01: 6 bit
;	||||||                     10: 7 bit
;	||||||                     11: 8 bit*
;	|||||+—————> parity type:   0: even*
;	|||||                       1: odd
;	|||++——————> parity mode:  00: check
;	|||                        01: force
;	|||                        10: don't check*
;	|||                        11: multidrop
;	||+————————> error mode:    0: character*
;	||                          1: block
;	|+—————————> RxD IRQ mode:  0: RxD ready*
;	|                           1: FIFO full
;	+——————————> RxD RTS mode:  0: off
;	                            1: on*
;	* = default setting
;
;	xxxxxxxx ——> MR2 settings
;	||||||||
;	||||++++———> stop bit length
;	||||
;	|||+———————> TxD CTS mode:  0: off
;	|||                         1: on
;	||+————————> TxD RTS mode:  0: off
;	||                          1: on
;	++—————————> channel mode: 00: normal
;	                           01: auto echo 
;	                           10: local loop
;	                           11: remote loop
;
dr_srb   =%1001                ;ch B status (R)...
;
;	xxxxxxxx
;	||||||||
;	|||||||+———> 1: RxD FIFO not empty
;	||||||+————> 1: RxD FIFO full
;	|||||+—————> 1: TxD FIFO not empty
;	||||+——————> 1: TxD FIFO empty
;	|||+———————> 1: RxD overrun
;	||+————————> 1: parity error
;	|+—————————> 1: framing error
;	+——————————> 1: break received
;
dr_csrb  =dr_srb               ;ch B clock select (W)...
;
;	xxxxxxxx
;	||||||||
;	||||++++———> TxD baud rate & BRG source
;	++++———————> RxD baud rate & BRG source
;
dr_crb   =%1010                ;ch B command (W)...
;
;	xxxxxxxx
;	||||||||
;	||||||++———>   00: no operation
;	||||||         01: enable receiver
;	||||||         10: disable receiver
;	||||||         11: illegal operation
;	||||++—————>   00: no operation
;	||||           01: enable transmitter
;	||||           10: disable transmitter
;	||||           11: illegal operation
;	++++———————> 0000: no operation
;	             0001: select MR1
;	             0010: reset & disable receiver
;	             0011: reset & disable transmitter
;	             0100: reset error status
;	             0101: reset break IRQ
;	             0110: start TxD break
;	             0111: stop TxD break
;	             1000: assert RTS
;	             1001: deassert RTS
;	             1010: enable C/T timeout mode
;	             1011: select MR0
;	             1100: disable C/T timeout mode
;	             1101: undefined
;	             1110: undefined
;	             1111: undefined
;
dr_rhrb  =%1011                ;ch B RxD holding (R)
dr_thrb  =dr_rhrb              ;ch B TxD holding (W)
dr_usrdf =%1100                ;user-defined (R/W)
dr_opcr  =%1101                ;output port configuration (W)
dr_ipsr  =dr_opcr              ;input port status (R)
dr_sctc  =%1110                ;start C/T command (R)
dr_sopbc =dr_sctc              ;set output port bits command (W)
dr_rctc  =%1111                ;stop C/T command (R)
dr_ropbc =dr_rctc              ;reset output port bits command (W)
;
	.end

[norby]

8BIT wrote:

norby wrote:

Is the ENC28J60 any good?

The only problem I've had with the ENC28J60 module is sometimes it does not start up. I have to re-initialize it or even power cycle it for it to start. Once running, it runs very well. That issue may be caused by me and not the module, I just haven't had it happen frequently enough to drive me to investigate it.

Daryl

After much consideration and trying this weekend I have decided to skip SPI and the ENC28J60 in this version of the SBC. But it is definetly on the top of my list for next version.

I looked at you 65SPI and it looks like a nice device. Do you have any plans to convert the code to something else like VHDL? Not that I don't want to support you efforts by buying from you - but I would like to keep the chip count down - possibly buy incorporating it into a bigger chip.

/norby

[norby]

BigDumbDinosaur wrote:

norby wrote:

After reading the DS1511 datasheet I get the impression that VBAUX can actually handle +5V.
Page 2 "Recommended DC operating conditions"
Auxiliary Battery Voltage (note 3) VBaux
Says 5.3 V max.

Later in the text they talk about 2.5V - 3.7V for VBAUX but I guess that applies to the 3.3V (W) version.

As I said, Dallas' data sheets can be confusing. Whomever was responsible for their technical writing needed to be reassigned to janitorial service.

Several years ago, I talked to Maxim's tech support on this subject and was told that Vbaux was intended to be powered by a CR2032 battery or similar. I tried to pin the guy down on whether Vbaux could be directly powered off the +5VSB output of an ATX power supply, but all he would say was it was intended to be powered by a 3.3 volt battery. So I decided that he was trying to tell me that the 5.3 volt max was probably a "do not exceed" value and that Vbaux really should be powered by 3.3 volts. Hence the voltage divider.

Quote:

I just breadboarded the circuit you described, with and without a voltage divider and both seems to work perfectly. The only gotcha is that pushing /KS again will not automatically power off the system. It seems that it can be handled in software though.

There's a defined sequence to follow in order to power down under software control. You will need to peruse the data sheet for the details, starting on page 17. Look at the PAB bit in register $0E.

It's also possible to detect closure of the power push button while the system is powered, and in fact, you can arrange for that closure to generate an IRQ. In such a case, the IRQ could cause the operating system kernel to initiate an orderly system shutdown when the power push button is pressed, like what happens with Linux or Window$.

Quote:

After reading the datasheet I got the impression that the watchdog and irq where unrelated, I guess I was wrong, I changed my schematic - /RST tied to VCC via a resistor.

The DS1511 can be programmed so that an underflow of the watchdog will either generate an IRQ or toggle /RST. In my application, I have the watchdog timing out at 10ms intervals, but automatically reloading and continuing. Hence it isn't necessary to restart the timer each time it underflows and interrupts.

Again thank you for all the clearifications, you seem to have spend quite some energy on this chip

I have incorporated all you suggestions into my schematic. I think I have reached a point where I don't what to change anything... at least for this version of the SBC.

Comments are welcome.

/norby

[BigDumbDinosaur]

norby wrote:

Again thank you for all the clearifications, you seem to have spend quite some energy on this chip

Not really. I put far more time into the 26C92 and 53C94, even though their data sheets are more lucid than those of Maxim.

Quote:

I have incorporated all you suggestions into my schematic. I think I have reached a point where I don't what to change anything... at least for this version of the SBC.

• I see two Ø2 connections attached to the CPLD. The one at the GCLK1 input (pin 83) makes sense, as your flops and state machines would be clocked from that input. What's the purpose of the Ø2 connection at the IO3 input (pin 20)?
• You have ABORT and BE on the 65C816 sharing a common pullup resistor. I'm not aware of any adverse effects that such an arrangement might cause, but it does prevent those inputs from being used for their intended purposes. If you can spare the room, I suggest separating the two (take a look at resistor networks in SIPP form to conserve PCB space) and connecting ABORT to an unused CPLD input so you can experiment with it.
• What is the function of IC20P?
• I really don't recommend the use of the MAX3232 in your application. That device was developed to implement serial transceiver functions where economy of power consumption is paramount. Maxim sacrificed drive strength and noise immunity to minimize power consumption. You will be powering your unit from a PC type power supply, so the value of the MAX3232 in your application is zilch.
  
  The MAX238 is a better choice, as its charge pump circuit produces a more robust output, which makes it do a better job of driving the serial link. Plus you get support for both serial channels in a single package, will consume less board real estate (fewer capacitors) and as a bonus, a single MAX238 costs less that two MAX3232s. Order Maxim part number MAX238CWG+ for the SOIC24 version or MAX238CNG+ for the PDIP24 package. Pinout is the same for both devices.
• In some cases, TIA-232 devices may required that their DSR inputs be asserted as a condition of establishing communication. You can take care of this by providing a DTR output from your serial hardware. Make the connection at the MAXxxx V+ pin. See attached.
  

  

  MAX238 Typical Interface (from POC V1.1)

• Resistors that drive LEDs from Vcc should probably be 470 ohms. The value you selected drives most LEDs harder than necessary.

[cbscpe]

Hi Nobrby,

nice design. I see that you use a CF Card as mass storage. As I'm currently fighting with interfacing the W65C816 to the CF Card, I wanted to let you know my findings. First if you are using True IDE mode (PIN9 to ground) then you can not hot-swap the compact flash, because a newly inserted card will not be set to True IDE mode (when it powers up it will see Pin9 floating before it is fully inserted). You need to power-cycle the card. So either you add high-side switch (or as I use a AO3401) or a switch to power cycle the the CF Card. To not reset the CPU when you power-cycle the CF Card you must make sure that you separate the /RES of the CF Card from the reset line, e.g. by using a dedicated output of the reset circuitry.

Also it seems compact flash cards are very sensitive to address hold time form /IORD and /IOWR going high and in True IDE Mode the address consists not only of A0, A1, A2. /CS0 and /CS1 (Pin7 and Pin 32) are considered as as well as part of the address. When using a fast CPLD (or GAL in my case) /CS0 is de-asserted to soon (at least for the CF Cards I'm currently testing with) you need to "stretch" it or delay de-assertion. Also as during the read and write buffer the CF Card "counts" the number of /IORD and /IOWR pulses. You should pay attention that there are no glitches or extra /IORD or /IOWR. In may case I had to use a dedicated circuit that generates /IOWR and /IORD only when the CF Card is selected.

I have also a question. Are you using Eagle as CAD? And yes where did you get the library for the 65Cxxx devices from? I would really need them to finally properly document my systems.

Peter

[norby]

BigDumbDinosaur wrote:

I see two Ø2 connections attached to the CPLD. The one at the GCLK1 input (pin 83) makes sense, as your flops and state machines would be clocked from that input. What's the purpose of the Ø2 connection at the IO3 input (pin 20)?

I'm/was uncertain if the signal going into GCLK1 can also be referenced like a normal input pin inside to CPLD code. But I guess it can be.

BigDumbDinosaur wrote:

You have ABORT and BE on the 65C816 sharing a common pullup resistor. I'm not aware of any adverse effects that such an arrangement might cause, but it does prevent those inputs from being used for their intended purposes. If you can spare the room, I suggest separating the two (take a look at resistor networks in SIPP form to conserve PCB space) and connecting ABORT to an unused CPLD input so you can experiment with it.

I'm using 1206 SMD resisters so board space is not really an issue here. I have changed the schematic to what you have proposed.

BigDumbDinosaur wrote:

What is the function of IC20P?

This is just the power connection block for IC20, the CPLD, It can do some fancy level shifting depending on what you feed it on the VCCIO pins - at least that is what I think I see in the data sheet

BigDumbDinosaur wrote:

I really don't recommend the use of the MAX3232 in your application. <snip a lot of good points.... snip>

I have changed the design to use a SOIC MAX238 as you suggest.

BigDumbDinosaur wrote:

Resistors that drive LEDs from Vcc should probably be 470 ohms. The value you selected drives most LEDs harder than necessary.

Changed, thanks!


During my own review I encountered one thing that I hope you can shed some light on. Currently I have the direction pin on the 74ABT245 (IC5) connected to the /WE output from the CPLD. Would it be better/mandatory to connect it directly to the R/W pin from the CPU?

As always input is welcome!


Attached it the latest version of the schematic.

/norby

[norby]

cbscpe wrote:

Hi Nobrby,

nice design. I see that you use a CF Card as mass storage. As I'm currently fighting with interfacing the W65C816 to the CF Card, I wanted to let you know my findings. First if you are using True IDE mode (PIN9 to ground) then you can not hot-swap the compact flash, because a newly inserted card will not be set to True IDE mode (when it powers up it will see Pin9 floating before it is fully inserted). You need to power-cycle the card. So either you add high-side switch (or as I use a AO3401) or a switch to power cycle the the CF Card. To not reset the CPU when you power-cycle the CF Card you must make sure that you separate the /RES of the CF Card from the reset line, e.g. by using a dedicated output of the reset circuitry.

Also it seems compact flash cards are very sensitive to address hold time form /IORD and /IOWR going high and in True IDE Mode the address consists not only of A0, A1, A2. /CS0 and /CS1 (Pin7 and Pin 32) are considered as as well as part of the address. When using a fast CPLD (or GAL in my case) /CS0 is de-asserted to soon (at least for the CF Cards I'm currently testing with) you need to "stretch" it or delay de-assertion. Also as during the read and write buffer the CF Card "counts" the number of /IORD and /IOWR pulses. You should pay attention that there are no glitches or extra /IORD or /IOWR. In may case I had to use a dedicated circuit that generates /IOWR and /IORD only when the CF Card is selected.

I have also a question. Are you using Eagle as CAD? And yes where did you get the library for the 65Cxxx devices from? I would really need them to finally properly document my systems.

Peter

Hi Peter

Thank you for you input. I do intend to run it in TrueIDE mode 8bit, but hotswapping is not on the agenda so I think I can live with the limitations you descibed.

I'm very interested in your input to weather this will work or not. Actually I kinda threw the CF card design in there after reading your posts about the subject. Input that will make this design actually work is very welcome.

I'm using eaglecad and I couldn't find a WDC library so I made it myself. It is attached here, but please check it berfor using and please report back errors to me! It is not complete, currently it has 65816 DIP/PLCC, 6502 PLCC, 6522 DIP/PLCC and 65SPI PLCC (not really WDC but close enough for me...). All PLCC versions are for a through hole socket.

If there is something in the lib you need let me know I and can add it.

/norby

[lordbubsy]

Thanks for uploading the Eagle library. I have also made my own EAGLE CAD library for the IC’s I needed.

• 65SPI PLCC
• MAX3100 DIP
• SC26C92 PLCC
• W65C02S DIP
• W65C22S DIP
• W65C51N DIP
• W65C816S DIP

At least there are a few which are not in your library, so perhaps it is helpful.

[cbscpe]

Hi norby
Thanks for the library. I will soon start to draw the schematic and will let you know how it works.

As for the CF Card Interface it works. In fact I got it working approx. one hour before my first post to this thread. I use the following schematic

cf-card-decode.pdf

CF Card Decode

(14.73 KiB) Downloaded 102 times

The /DISK signal is only asserted for a small 16-byte IO Window. The decoder (a 7ns GAL) only uses address lines and VDA to create the /DISK signal without using PHI2 etc. This same signal goes to /CS0 of the CF-Card. /IOWR and IORD are qualified via PHI2. So they are asserted only during PHI2 High-phase and de-asserted before the decoder de-asserts /DISK. Basic read/write sector routines already work with a CPU Clock of 4MHz. Higher clock speed should be possible. Currently I'm writing the bootloader for the OS.

Regards

Peter

[BigDumbDinosaur]

norby wrote:

BigDumbDinosaur wrote:

I see two Ø2 connections attached to the CPLD. The one at the GCLK1 input (pin 83) makes sense, as your flops and state machines would be clocked from that input. What's the purpose of the Ø2 connection at the IO3 input (pin 20)?

I'm/was uncertain if the signal going into GCLK1 can also be referenced like a normal input pin inside to CPLD code. But I guess it can be.

GCLK1 is like any other input. All internal timing references that depend on the state of Ø2 should refer to this input. If you have any logic that becomes active/valid on Ø2 low, it might not be a bad idea to derive a Ø1 clock from the /Q output of your clock generator flop and connect that signal to the GCLK2 input on your CPLD. Generating Ø1 inside the CPLD uses product terms (you have to synthesize a flop) and causes Ø2 and Ø1 to slightly overlap.

Quote:

During my own review I encountered one thing that I hope you can shed some light on. Currently I have the direction pin on the 74ABT245 (IC5) connected to the /WE output from the CPLD. Would it be better/mandatory to connect it directly to the R/W pin from the CPU?

DIR on the '245 should be driven by RWB from the MPU. As you have it now, two timing issues will arise. The key one is that the '245 will lag the change in data direction by the prop time of the CPLD, which will become problematic as you crank up the clock rate. The other issue is that if you have your /WE output from the CPLD being qualified by Ø2 high (as you should), the '245's direction will not be set up until Ø2 high plus the CPLD prop time plus the '245's state change time.

Incidentally, I see some connections on the '245 and your '573 bank latch that don't seem to go anywhere.

[norby]

BigDumbDinosaur wrote:

norby wrote:

BigDumbDinosaur wrote:

I see two Ø2 connections attached to the CPLD. The one at the GCLK1 input (pin 83) makes sense, as your flops and state machines would be clocked from that input. What's the purpose of the Ø2 connection at the IO3 input (pin 20)?

I'm/was uncertain if the signal going into GCLK1 can also be referenced like a normal input pin inside to CPLD code. But I guess it can be.

GCLK1 is like any other input. All internal timing references that depend on the state of Ø2 should refer to this input. If you have any logic that becomes active/valid on Ø2 low, it might not be a bad idea to derive a Ø1 clock from the /Q output of your clock generator flop and connect that signal to the GCLK2 input on your CPLD. Generating Ø1 inside the CPLD uses product terms (you have to synthesize a flop) and causes Ø2 and Ø1 to slightly overlap.

Quote:

During my own review I encountered one thing that I hope you can shed some light on. Currently I have the direction pin on the 74ABT245 (IC5) connected to the /WE output from the CPLD. Would it be better/mandatory to connect it directly to the R/W pin from the CPU?

DIR on the '245 should be driven by RWB from the MPU. As you have it now, two timing issues will arise. The key one is that the '245 will lag the change in data direction by the prop time of the CPLD, which will become problematic as you crank up the clock rate. The other issue is that if you have your /WE output from the CPLD being qualified by Ø2 high (as you should), the '245's direction will not be set up until Ø2 high plus the CPLD prop time plus the '245's state change time.

Incidentally, I see some connections on the '245 and your '573 bank latch that don't seem to go anywhere.

Which ones? The /GOE and ALE signals? They are connected to the CPLD...

I connected the /Q of the clock flip flop to GCLK2 of the CPLD, for lack of a better name I called it /PHI2.

I also changed the DIR pin of the '245 to use the MPU's R/W signal directly.

I have attached sheet 1 which is the only one that has been updated this time.

/norby

[norby]

cbscpe wrote:

Hi norby
Thanks for the library. I will soon start to draw the schematic and will let you know how it works.

As for the CF Card Interface it works. In fact I got it working approx. one hour before my first post to this thread. I use the following schematic

cf-card-decode.pdf

The /DISK signal is only asserted for a small 16-byte IO Window. The decoder (a 7ns GAL) only uses address lines and VDA to create the /DISK signal without using PHI2 etc. This same signal goes to /CS0 of the CF-Card. /IOWR and IORD are qualified via PHI2. So they are asserted only during PHI2 High-phase and de-asserted before the decoder de-asserts /DISK. Basic read/write sector routines already work with a CPU Clock of 4MHz. Higher clock speed should be possible. Currently I'm writing the bootloader for the OS.

Regards

Peter

Hi Peter

I'm looking forward to your schematic.

/norby