norby wrote:
After reading the DS1511 datasheet I get the impression that VBAUX can actually handle +5V.
Page 2 "Recommended DC operating conditions"
Auxiliary Battery Voltage (note 3) VBaux
Says 5.3 V max.
Later in the text they talk about 2.5V - 3.7V for VBAUX but I guess that applies to the 3.3V (W) version.
As I said, Dallas' data sheets can be confusing. Whomever was responsible for their technical writing needed to be reassigned to janitorial service.
Several years ago, I talked to Maxim's tech support on this subject and was told that
Vbaux was intended to be powered by a CR2032 battery or similar. I tried to pin the guy down on whether
Vbaux could be directly powered off the
+5VSB output of an ATX power supply, but all he would say was it was intended to be powered by a 3.3 volt battery. So I decided that he was trying to tell me that the 5.3 volt max was probably a "do not exceed" value and that
Vbaux really should be powered by 3.3 volts. Hence the voltage divider.
Quote:
I just breadboarded the circuit you described, with and without a voltage divider and both seems to work perfectly. The only gotcha is that pushing /KS again will not automatically power off the system. It seems that it can be handled in software though.
There's a defined sequence to follow in order to power down under software control. You will need to peruse the data sheet for the details, starting on page 17. Look at the
PAB bit in register
$0E.
It's also possible to detect closure of the power push button while the system is powered, and in fact, you can arrange for that closure to generate an IRQ. In such a case, the IRQ could cause the operating system kernel to initiate an orderly system shutdown when the power push button is pressed, like what happens with Linux or Window$.
Quote:
After reading the datasheet I got the impression that the watchdog and irq where unrelated, I guess I was wrong, I changed my schematic - /RST tied to VCC via a resistor.
The DS1511 can be programmed so that an underflow of the watchdog will either generate an IRQ or toggle /RST. In my application, I have the watchdog timing out at 10ms intervals, but automatically reloading and continuing. Hence it isn't necessary to restart the timer each time it underflows and interrupts.
See following code for a set of definitions for the DS1511 and the 26C92.
Code:
;================================================================================
;
;DALLAS DS1511 REAL-TIME CLOCK DEFINITIONS
;
nr_rtc =32 ;total registers ($14-$1F reserved)
;
;
; register offsets...
;
wr_sect =$00 ;TOD seconds ($00-$59 BCD)
wr_mint =$01 ;TOD minutes ($00-$59 BCD)
wr_hrst =$02 ;TOD hour ($00-$23 BCD)
wr_dowt =$03 ;day of week ($01-$07 BCD)
wr_datt =$04 ;date ($01-$31 BCD)
wr_mon =$05 ;month & control...
;
; xxxxxxxx
; ||||||||
; |||+++++———> month ($01-$12 BCD)
; ||+————————> 1: enable 32 Khz at SQW when on battery
; |+—————————> 0: enable 32 KHz at SQW when on Vcc
; +——————————> 0: enable oscillator
;
wr_yrlo =$06 ;year LSB ($00-$99 BCD)
wr_yrhi =$07 ;year MSB ($00-$39 BCD)
wr_seca =$08 ;alarm seconds & IRQ control...
;
; xxxxxxxx
; ||||||||
; |+++++++———> alarm seconds ($00-$59 BCD)
; +——————————> 1: IRQ once per second
;
wr_mina =$09 ;alarm minutes & IRQ control...
;
; xxxxxxxx
; ||||||||
; |+++++++———> alarm minutes ($00-$59 BCD)
; +——————————> 1: IRQ when TOD secs = alarm secs
;
wr_hrsa =$0a ;alarm hour & IRQ control...
;
; x0xxxxxx
; | ||||||
; | ++++++———> alarm hour ($00-$23 BCD)
; +——————————> 1: IRQ when TOD secs & mins = alarm secs & mins
;
wr_dowa =$0b ;alarm date/day & IRQ control...
;
; xxxxxxxx
; ||||||||
; ||++++++———> alarm day ($01-$07 BCD) or date ($01-$31 BCD)
; |+—————————> 0: alarm date set
; | 1: alarm day set
; +——————————> 0: IRQ when TOD & day/date = alarm TOD & day/date
; 1: IRQ when TOD = alarm time
;
wr_wdms =$0c ;watchdog millisecs*10 ($00-$99 BCD)
wr_wds =$0d ;watchdog seconds ($00-$99 BCD)
wr_cra =$0e ;control register A...
;
; xxxxxxxx
; ||||||||
; |||||||+———> 1: IRQ pending (read only)
; ||||||+————> 1: IRQ = watchdog timer
; |||||+—————> 1: IRQ = kickstart (read only)
; ||||+——————> 1: IRQ = TOD alarm
; |||+———————> 0: PWR pin = active low
; ||| 1: PWR pin = high-Z
; ||+————————> 0: PWR pin = high-Z wo/Vcc present
; || 1: PWR pin = active low wo/Vcc present
; |+—————————> 1: aux external battery low (read only)
; +——————————> 1: external battery low (read only)
;
wr_crb =$0f ;control register B...
;
; x0xxxxxx
; | ||||||
; | |||||+———> 0: watchdog generates IRQ
; | ||||| 1: watchdog generates reset
; | ||||+————> 1: watchdog IRQ/reset enabled
; | |||+—————> 1: kickstart IRQ enabled
; | ||+——————> 1: TOD alarm IRQ enabled
; | |+———————> 1: TOD alarm wakeup enabled
; | +————————> 1: NVRAM address autoincrement enabled
; +——————————> 0: TOD & date register update disabled
; 1: TOD & date register update enabled
;
wr_nvra =$10 ;NVRAM address port ($00-$FF)
wr_rsva =$11 ;reserved
wr_rsvb =$12 ;reserved
wr_nvrd =$13 ;NVRAM data port
;
;================================================================================
;
;NXP26C92 DUAL ACIA DEFINITIONS
;
nc_c92a =2 ;number of channels
nr_c92a =8 ;registers per channel
nr_26c92 =nr_c92a*nc_c92a ;total registers
;
;
; register offsets...
;
dr_mra =%0000 ;ch A mode select...
;
; xxxx0xxx ——> mode 0 settings
; |||| |||
; |||| +++———> baud rate extend: 000: normal
; |||| 001: extended mode 1
; |||| 100: extended mode 2
; ||++———————> TxD FIFO IRQ level: 00: 8
; || 01: 4
; || 10: 6
; || 11: 1
; |+—————————> RxD FIFO IRQ level: 0: 1-5: see also MR1:6
; | 1: 6-8: see also MR1:6
; +——————————> RxD watchdog: 0: disable
; 1: enable
;
; xxxxxxxx ——> MR1 settings
; ||||||||
; ||||||++———> data format: 00: 5 bit
; |||||| 01: 6 bit
; |||||| 10: 7 bit
; |||||| 11: 8 bit*
; |||||+—————> parity type: 0: even*
; ||||| 1: odd
; |||++——————> parity mode: 00: check
; ||| 01: force
; ||| 10: don't check*
; ||| 11: multidrop
; ||+————————> error mode: 0: character*
; || 1: block
; |+—————————> RxD IRQ mode: 0: RxD ready*
; | 1: FIFO full
; +——————————> RxD RTS mode: 0: off
; 1: on*
; * = default setting
;
; xxxxxxxx ——> mode 2 settings
; ||||||||
; ||||++++———> stop bit length
; ||||
; |||+———————> TxD CTS mode: 0: off
; ||| 1: on
; ||+————————> TxD RTS mode: 0: off
; || 1: on
; ++—————————> channel mode: 00: normal
; 01: auto echo
; 10: local loop
; 11: remote loop
;
dr_sra =%0001 ;ch A status (R)...
;
; xxxxxxxx
; ||||||||
; |||||||+———> 1: RxD FIFO not empty
; ||||||+————> 1: RxD FIFO full
; |||||+—————> 1: TxD FIFO not empty
; ||||+——————> 1: TxD FIFO empty
; |||+———————> 1: RxD overrun
; ||+————————> 1: parity error
; |+—————————> 1: framing error
; +——————————> 1: break received
;
dr_csra =dr_sra ;ch A clock select (W)...
;
; xxxxxxxx
; ||||||||
; ||||++++———> TxD baud rate & BRG source
; ++++———————> RxD baud rate & BRG source
;
dr_cra =%0010 ;ch A command (W)...
;
; xxxxxxxx
; ||||||||
; ||||||++———> 00: no operation
; |||||| 01: enable receiver
; |||||| 10: disable receiver
; |||||| 11: illegal operation
; ||||++—————> 00: no operation
; |||| 01: enable transmitter
; |||| 10: disable transmitter
; |||| 11: illegal operation
; ++++———————> 0000: no operation
; 0001: select MR1
; 0010: reset & disable receiver
; 0011: reset & disable transmitter
; 0100: reset error status
; 0101: reset break IRQ
; 0110: start TxD break
; 0111: stop TxD break
; 1000: assert RTS
; 1001: deassert RTS
; 1010: enable C/T timeout mode
; 1011: select MR0
; 1100: disable C/T timeout mode
; 1101: undefined
; 1110: standby power mode
; 1111: normal power mode
;
dr_rhra =%0011 ;ch A RxD FIFO (R)
dr_thra =dr_rhra ;ch A TxD FIFO (W)
dr_ipcr =%0100 ;input port change (R)
dr_acr =dr_ipcr ;auxiliary control register (W)...
;
; xxxxxxxx
; ||||||||
; |||||||+———> 1: enable IP0 IRQ
; ||||||+————> 1: enable IP1 IRQ
; |||||+—————> 1: enable IP2 IRQ
; ||||+——————> 1: enable IP3 IRQ
; |+++———————> C/T setup:
; |
; | 654 Mode Source
; | ———————————————————————————————
; | 000 counter IP2
; | 001 counter TxD Ch 1 1X clock
; | 010 counter TxD Ch 2 1X clock
; | 011 counter Xtal/16
; | 100 timer IP2
; | 101 timer IP2/16
; | 110 timer Xtal
; | 111 timer Xtal/16
; | ———————————————————————————————
; |
; +——————————> 0: select BRG set #1 (38.4k max)
; 1: select BRG set #2 (19.2k max)
;
dr_imr =%0101 ;interrupt enable mask (W)...
;
; xxxxxxxx
; ||||||||
; |||||||+———> 1: enable ch A THR ready
; ||||||+————> 1: enable ch A RHR ready/FIFO full
; |||||+—————> 1: enable ch A change in break
; ||||+——————> 1: enable C/T ready
; |||+———————> 1: enable ch B THR ready
; ||+————————> 1: enable ch B RHR ready/FIFO full
; |+—————————> 1: enable ch B change in break
; +——————————> 1: enable IP0-IP3 state change
;
dr_isr =dr_imr ;interrupt status (R)...
;
; xxxxxxxx
; ||||||||
; |||||||+———> 1: ch A THR ready
; ||||||+————> 1: ch A RHR ready/FIFO full
; |||||+—————> 1: ch A change in break
; ||||+——————> 1: C/T ready
; |||+———————> 1: ch B THR ready
; ||+————————> 1: ch B RHR ready/FIFO full
; |+—————————> 1: ch B change in break
; +——————————> 1: IP0-IP3 state change
;
dr_crur =%0110 ;C/T MSB preset (W)
dr_crlr =%0111 ;C/T LSB preset (W)
dr_ctu =dr_crur ;C/T MSB value (R)
dr_ctl =dr_crlr ;C/T LSB value (R)
dr_mrb =%1000 ;ch B mode select...
;
; xxxx0000 ——> MR0 settings
; ||||
; ||++———————> TxD FIFO IRQ level: 00: 8
; || 01: 4
; || 10: 6
; || 11: 1
; |+—————————> RxD FIFO IRQ level: 0: 1-5: see also MR1:6
; | 1: 6-8: see also MR1:6
; +——————————> RxD watchdog: 0: disable
;
; xxxxxxxx ——> MR1 settings
; ||||||||
; ||||||++———> data format: 00: 5 bit
; |||||| 01: 6 bit
; |||||| 10: 7 bit
; |||||| 11: 8 bit*
; |||||+—————> parity type: 0: even*
; ||||| 1: odd
; |||++——————> parity mode: 00: check
; ||| 01: force
; ||| 10: don't check*
; ||| 11: multidrop
; ||+————————> error mode: 0: character*
; || 1: block
; |+—————————> RxD IRQ mode: 0: RxD ready*
; | 1: FIFO full
; +——————————> RxD RTS mode: 0: off
; 1: on*
; * = default setting
;
; xxxxxxxx ——> MR2 settings
; ||||||||
; ||||++++———> stop bit length
; ||||
; |||+———————> TxD CTS mode: 0: off
; ||| 1: on
; ||+————————> TxD RTS mode: 0: off
; || 1: on
; ++—————————> channel mode: 00: normal
; 01: auto echo
; 10: local loop
; 11: remote loop
;
dr_srb =%1001 ;ch B status (R)...
;
; xxxxxxxx
; ||||||||
; |||||||+———> 1: RxD FIFO not empty
; ||||||+————> 1: RxD FIFO full
; |||||+—————> 1: TxD FIFO not empty
; ||||+——————> 1: TxD FIFO empty
; |||+———————> 1: RxD overrun
; ||+————————> 1: parity error
; |+—————————> 1: framing error
; +——————————> 1: break received
;
dr_csrb =dr_srb ;ch B clock select (W)...
;
; xxxxxxxx
; ||||||||
; ||||++++———> TxD baud rate & BRG source
; ++++———————> RxD baud rate & BRG source
;
dr_crb =%1010 ;ch B command (W)...
;
; xxxxxxxx
; ||||||||
; ||||||++———> 00: no operation
; |||||| 01: enable receiver
; |||||| 10: disable receiver
; |||||| 11: illegal operation
; ||||++—————> 00: no operation
; |||| 01: enable transmitter
; |||| 10: disable transmitter
; |||| 11: illegal operation
; ++++———————> 0000: no operation
; 0001: select MR1
; 0010: reset & disable receiver
; 0011: reset & disable transmitter
; 0100: reset error status
; 0101: reset break IRQ
; 0110: start TxD break
; 0111: stop TxD break
; 1000: assert RTS
; 1001: deassert RTS
; 1010: enable C/T timeout mode
; 1011: select MR0
; 1100: disable C/T timeout mode
; 1101: undefined
; 1110: undefined
; 1111: undefined
;
dr_rhrb =%1011 ;ch B RxD holding (R)
dr_thrb =dr_rhrb ;ch B TxD holding (W)
dr_usrdf =%1100 ;user-defined (R/W)
dr_opcr =%1101 ;output port configuration (W)
dr_ipsr =dr_opcr ;input port status (R)
dr_sctc =%1110 ;start C/T command (R)
dr_sopbc =dr_sctc ;set output port bits command (W)
dr_rctc =%1111 ;stop C/T command (R)
dr_ropbc =dr_rctc ;reset output port bits command (W)
;
.end
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I put far more time into the 26C92 and 53C94, even though their data sheets are more lucid than those of Maxim.
