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GARTHWILSON
PostPosted: Wed Mar 01, 2023 7:56 am 
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I'll add to Michael's comment about the LCD backpack.  We have more discussion on the LCDs at viewtopic.php?p=91820#p91820 and following, and he shows more of his backpacks there too.

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and3rson
PostPosted: Wed Mar 01, 2023 5:47 pm 
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Jeff - thanks for the info, good to know it's normal - I was starting to get worried. :)

Michael, Garth - those backpacks are awesome. I entertained a possibility of doing serial communication with LCD via shift registers, but thought it was too complex... The articles you've shared actually make it look so simple! I will try to set up an LCD in this way once I get my basic setup working. So much cool things to do once I have my board!

I think for now I'll just piggy-back an additional '00 on top of my ADDR1 '00. This will allow me to cut LCD/EN and re-route it via 3 gates. In fact - I can actually put it over RW1 '00 - both have Ф2 on pin 5, so I'll just solder it in addition to VCC & GND, and only 2 jumpers will be needed: input from '138 & output to LCDEN.
Once I get the system working & get my second package from Mouser (with VIA & ACIA), I'll probably remove it and try to do serial communication with backpacks! This will probably be much cleaner than a bulky 16-wire ribbon that I'm going to use initially.

P. S. I think it's about time I split my Kicad schematic into multiple sheets... I tried resisting it (I really like having everything in front of me on a single page), but it's getting too crammed now. Maybe I'll simply try increasing sheet size to A3!


Attachments:
v09_lcd_fix_piggyback_bw.png
v09_lcd_fix_piggyback_bw.png [ 54.89 KiB | Viewed 114673 times ]

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barnacle
PostPosted: Wed Mar 01, 2023 9:19 pm 
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and3rson wrote:
Maybe I'll simply try increasing sheet size to A3!


To be honest, I would prefer that the default parts in Kicad were half the size they are; an A4 sheet fills far too quickly. But an A3 printed on A4 is quite legible... this design required one page for the logic and a second page just for the power connections and decoupling...

Neil


Attachments:
fake8080c-alu_core.pdf [182.03 KiB]
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and3rson
PostPosted: Thu Mar 02, 2023 12:08 pm 
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barnacle wrote:
and3rson wrote:
Maybe I'll simply try increasing sheet size to A3!


To be honest, I would prefer that the default parts in Kicad were half the size they are; an A4 sheet fills far too quickly. But an A3 printed on A4 is quite legible... this design required one page for the logic and a second page just for the power connections and decoupling...

Neil


Yeah, some parts are way too bulky. I had to shrink inputs/outputs of few logic gates just to be able to fit them in a tight space.

Meanwhile, I've been thinking about a possibility to have several programs on one ROM and to be able to develop & run them individually by having some software banking for ROM. I have lots of W27C512 (which fit 8x 8-KB ROM images) that I used with my C64s, and the idea of implementing the banking itself feels so cool. It can also be used to bank RAMs (although I don't have any needs for RAM banking yet.)

I've seen people on this forum suggesting to use '273, and it turned out to be a perfect solution: I'll simply have a byte somewhere in memory (possibly I/O region), to which I'll write the number of bank that I want to use.
On reset, '273 will also be reset, thus always starting with the first bank.
Here's a schematic I came up with:
Attachment:
File comment: Made with https://github.com/hneemann/Digital
v10_banking_bw.png
v10_banking_bw.png [ 94.84 KiB | Viewed 114632 times ]


There's a caveat though: '273 latches two times with this approach, once when data is invalid and once when the data is valid, so there's this "bad" section. I wonder if there are any other caveats with this.
Here's a rough timing diagram of how I think this is going to work (I hope my understanding of 6502 write timings is correct). I've also used Ф1 instead of Ф2 to save one inverter.
Attachment:
File comment: Made with https://wavedrom.com/
v10_banking_time.png
v10_banking_time.png [ 13.83 KiB | Viewed 114632 times ]


Schematic file:
Attachment:
File comment: Made with https://github.com/hneemann/Digital
rom_banking.zip [1.14 KiB]
Downloaded 51 times

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Michael
PostPosted: Thu Mar 02, 2023 1:33 pm 
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Speaking of banking... I was wondering if the 74HC670 "4x4 Register File" IC might be a relatively simple and elegant solution for mapping RAM or ROM into 64K address space? I'm just not sure how you could force a particular block of ROM into the $C000..$FFFF space during power-up in order to load initial or default values into the four register files. Anyway, food for thought...


Attachments:
74HC670.pdf [398.89 KiB]
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K8LH MMU excerpt.png
K8LH MMU excerpt.png [ 234.23 KiB | Viewed 114625 times ]
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BigEd
PostPosted: Thu Mar 02, 2023 4:00 pm 
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(Food for thought indeed - see perhaps also @hoglet's design for the 6809 over here.)
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GARTHWILSON
PostPosted: Thu Mar 02, 2023 8:52 pm 
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and3rson wrote:
There's a caveat though: '273 latches two times with this approach, once when data is invalid and once when the data is valid, so there's this "bad" section. I wonder if there are any other caveats with this.

The '273 is edge-triggered, triggering on the rising clock edge only, not both clock edges.  Did something escape my attention?

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and3rson
PostPosted: Thu Mar 02, 2023 10:15 pm 
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GARTHWILSON wrote:
and3rson wrote:
There's a caveat though: '273 latches two times with this approach, once when data is invalid and once when the data is valid, so there's this "bad" section. I wonder if there are any other caveats with this.

The '273 is edge-triggered, triggering on the rising clock edge only, not both clock edges.  Did something escape my attention?


What I meant is that
Code:
AND(Ф1, NOT(/EN))
will have two rising edges during each full clock cycle, since "address valid" spans across two high half-cycles of Ф1: first time data is not valid, and second time data is valid.
/EN comes from I/O my address decoder ('138) and is not synced with Ф, so it's low as long as the address line is valid.
"Latch" in my diagram is an input to clock pin of '273. I think I should have called it "74x273 clock" in my diagram.

EDIT: Michael - thanks for sharing: the more I dig through 7400 family, the more cool chips I find, so it's always nice to see some examples how they're actually used! I never knew there are entire MxN RAMs in 7400.

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and3rson
PostPosted: Thu Mar 02, 2023 10:47 pm 
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Great success - I've managed to squeeze an extra NAND into my board! And it's still less than 100 cm² (15.5 in²). Diptrace's autorouter was struggling with this design, so I had to move some chips around a little bit in order to successfully route all traces.
Also, I forgot to mention that Diptrace works perfectly in Wine! It's even mentioned on their website. I've been running it on my GNU/Linux under Wayland without a single problem.

I also hid some caps under chips - I'm having all of them socketed (event oscillator, using a machine-tooled P14P socket with all but 4 outmost pins removed with a thin screwdriver), so there's some extra clearance to place stuff underneath.
I cloud have hidden the resistors as well, but I really like boards where resistors are all nicely lined up and visible. I also kept some caps visible for the same reason.

Additionally, I've manually traced decoupling capacitors for this version. I've made a mistake in a previous design by allowing autorouter to do this, and as expected - it didn't wire them to where I wanted. Hindsight is 20/20. :D

Finally, I'm considering an option of feeding a 9V input to the board so that I can pass it over to the extension header and have a daughterboard with 8580r5 SID & a 1/8" headphone jack. I'm using a switching Traco Power RST 1-2450 instead of a 7805 regulator, so it should be fine with 9V input.

I've also increased my sheet size to A3 to have some extra breathing space. I like how the schematic looks now!

EDIT: Received an email from Mouser that my package shipment has been released. Looking forward to receiving my VIA & ACIA!
EDIT 2: I'm also planning to order several low-profile Aries ZIF sockets (DIP-28), seems like they might save me some space in my quest for cheap PCB manufacturing.


Attachments:
v10.png
v10.png [ 1003.19 KiB | Viewed 114574 times ]
v10_unrouted_bw.png
v10_unrouted_bw.png [ 63.61 KiB | Viewed 114574 times ]
v10_routed_bw.png
v10_routed_bw.png [ 93.56 KiB | Viewed 114574 times ]
v10_3d.jpg
v10_3d.jpg [ 112.52 KiB | Viewed 114574 times ]

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and3rson
PostPosted: Sat Mar 04, 2023 3:22 pm 
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Okay, today is the big day for me. I've got a big update!

My PCB has arrived this morning:

Attachment:
v09_printed1.jpg
v09_printed1.jpg [ 169.97 KiB | Viewed 114527 times ]

Attachment:
v09_printed2.jpg
v09_printed2.jpg [ 240.41 KiB | Viewed 114527 times ]


I was almost shaking when they handed it over to me. My first real PCB ever, what a feeling to have my design manufactured in real life!
I've also bought a simple 8-line digital analyzer (Saleae-compatible). I wish I've got a 16-line model - I could really use a spare clock line! But I've decided to try with 8 lines first, and simply use D0 as clock. This would mean that I'd lose 1 data line, but I really wanted to see if anything would be happening on at the data line at all.

I've assembled a thing and witnessed my SBC in its full glory:
Attachment:
v09_printed3.jpg
v09_printed3.jpg [ 177.25 KiB | Viewed 114527 times ]

(I'm currently using a DIP-28 SRAM, so I had to make simple adapter to insert it into my DIP-32 socket.)

At this point, I was EXTREMELY happy I've added pin headers for major CPU lines (including data bus & Ф2). Connecting an analyzer was a piece of cake:

Attachment:
v09_printed4.jpg
v09_printed4.jpg [ 198.11 KiB | Viewed 114527 times ]


I've then flashed my W27C512 with a simple program (vector setup & zeropage excluded for brevity) that adds $22 + $66:

Code:
init:
    ; sei
    ; cli

rep:
    ; V0 & V1 are 1-byte variables in zeropage (addresses $03 and $04)
    lda #$22
    sta V0
    lda #$66
    adc V0
    sta V1
    jmp rep


I then set my clock mode to manually triggered (using JP1) to step 1 cycle at a time using a button, launched Saleae analyzer UI (it worked out of the box on my Arch), and held my breath.

I hit "Step" switch several times, and I was presented with this absolute beauty:
Attachment:
v09_add_numbers.png
v09_add_numbers.png [ 157.62 KiB | Viewed 114527 times ]


Here's the dump:
Code:
name               type    start_time    duration          data
Simple Parallel    data    0.660707      2.25e-06          0x00000000000000E0
Simple Parallel    data    1.34691575    5e-07             0x00000000000000E0
Simple Parallel    data    2.000103      4.99999999e-07    0x00000000000000E0
Simple Parallel    data    2.64241125    5e-07             0x0000000000000048
Simple Parallel    data    3.3433495     5e-07             0x00000000000000E4
Simple Parallel    data    3.98544175    5e-07             0x00000000000000F0
Simple Parallel    data    4.75634       5e-07             0x00000000000000E4
Simple Parallel    data    5.532079      4.99999999e-07    0x0000000000000000 <======\
Simple Parallel    data    7.202979      4.99999999e-07    0x00000000000000E0 <===== Init vector value
Simple Parallel    data    7.859063      5e-07             0x00000000000000A8 <===== LDA (zp), should be $A9 (see explanation below)
Simple Parallel    data    8.77373775    4.99999998e-07    0x0000000000000022 <===== $22
Simple Parallel    data    11.8429005    4.99999998e-07    0x0000000000000084 <===== STA (zp)
Simple Parallel    data    12.5692233    5e-07             0x0000000000000002 <===== V0
Simple Parallel    data    13.6989845    5e-07             0x0000000000000022 <= write to RAM
Simple Parallel    data    14.6416862    5.00000002e-07    0x00000000000000A8 <===== LDA (zp), should be $A9
Simple Parallel    data    15.5184153    5e-07             0x0000000000000066 <===== $66
Simple Parallel    data    18.1610468    4.99999998e-07    0x0000000000000064 <===== ADC (zp)
Simple Parallel    data    20.696395     5.00000002e-07    0x0000000000000002 <====== V0
Simple Parallel    data    22.3814475    5.00000002e-07    0x0000000000000022 <= read from RAM
Simple Parallel    data    23.2602338    5.00000002e-07    0x0000000000000084 <===== STA (zp), should be $85
...
(at this point, I just sat for a whole minute, not being able to fully comprehend what did just happen - did I REALLY just see $22 and $66?!)
...
Simple Parallel    data    94.2452823    4.99999995e-07    0x0000000000000004 <===== V1
Simple Parallel    data    95.0413205    4.99999995e-07    0x0000000000000088 <===== Result of adding $22 + $66 (!)
Simple Parallel    data    96.899481     4.99999995e-07    0x000000000000004C <===== JMP to absolute
Simple Parallel    data    107.656872    5.00000009e-07    0x0000000000000000 <======\
Simple Parallel    data    109.788213    4.99999995e-07    0x00000000000000E0 <===== $E000 (ROM start)


IT WORKS! Address & read-write selectors (NAND glue) seems to behave just as they should!

You'll notice that the values don't match the actual opcodes (e. g. STA (zp) has opcode $85, but it's shown as $84 in my dump). This is because I've sacrificed D0 (lowest data line bit) in favor of feeding Ф2 to analyzer, so all captured values are rounded down to closest even value (D0 is always low).

I'm still sitting here in awe. Need a breather to proceed with connecting LCD. :D

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plasmo
PostPosted: Sat Mar 04, 2023 5:27 pm 
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Congratulations!
I’ve delivered literally thousands of computers in my career, it is the same breathless thrill every time. Thanks for sharing.
Bill
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BigEd
PostPosted: Sat Mar 04, 2023 6:25 pm 
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Excellent result! Thanks for sharing.
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barnacle
PostPosted: Sat Mar 04, 2023 8:12 pm 
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Congratulations!

It's always a good feeling when you bring up a board of your own design (and even better if it works first time :mrgreen: )

Neil
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Michael
PostPosted: Sat Mar 04, 2023 10:44 pm 
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Congrats', Andrew. Thanks for sharing a wonderful and exciting moment.

May I ask what's goin' on with the RAM?

Cheerful regards...
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and3rson
PostPosted: Sun Mar 05, 2023 3:15 pm 
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Thanks everyone! This wouldn't have been possible without all the help & support from this wonderful community.

Michael - that's a small DIP-28 to DIP-32 SRAM adapter, my AS6C1008 hasn't arrived yet, so I'm sticking to a 32Kx8 SRAM that I had.

I'm having a new problem now: the LCD.

I've added an additional 74HC00 on top of my RW1 so that I could convert LCD/EN into LCDEN and sync it with Ф2:
Attachment:
File comment: "Oh God, please, take it off me"
nand_piggyback.jpg
nand_piggyback.jpg [ 173.36 KiB | Viewed 114425 times ]

I've then rewired a low-active LCD/EN to to through this NAND and become LCD/EN as described here:
http://www.6502.org/mini-projects/optrexlcd/lcd6502.gif

And this is where all the weird stuff started happening.

The screen is initialized, but I can only see the garbage being printed:
Attachment:
lcd_garbage.jpg
lcd_garbage.jpg [ 185.15 KiB | Viewed 114425 times ]

(The string I'm attempting to print is "ABCDEFGH01234567".)

No matter what I tried, I couldn't produce any actual characters. The screen initializes, the cursor advances, but the garbage is always there.
I've tried clocking my SBC at 2MHz, 1.8432MHz, 1MHz, 500KHz, 100KHz, 10KHz, 1KHz, and even 100Hz - it's still the same.
Writing to HD44780's control register still works fine, I can read the busy flag & the DDRAM address just fine.

Now, here's the weirdest part: if I connect a wire longer than ~5 inches to Ф2, leaving the other way unconnected, the LCD initialization commands don't seem to have any effect, but writing to data register still advances the caret (although text is not visible), because if I read the control register, I can see that the DDRAM address has increased).
It happens whenever I connect a piece of wire, an oscilloscope probe, or a digital analyzer to either of the following places:
- Ф2;
- Between 2nd & 3rd quarters of NAND (http://www.6502.org/mini-projects/optrexlcd/lcd6502.gif);
- Directly to LCD's Enable pin.

I thought there was some voltage drop or extra capacitance on Ф2, but my scope still shows sharp edges on it. Additionally, the CPU still works normally, and LCD even seems to properly clear the busy flag (because my CPU doesn't hang on LCDBUSY routine).

Attachment:
lcd_weirdness.png
lcd_weirdness.png [ 48.38 KiB | Viewed 114425 times ]


In all of the above cases, I never saw any noise or voltage drop on Ф2 with my scope, and my digital analyzer always showed correct values of data bus at all times.

I've also tried adding filters on LCD's power terminals & Enable pin - no luck. Is there anything else I need to do to make the Enable pin work properly? It seems to be overly sensitive or something.
I also tried using 7805 instead of my TSR 1-2450.
Finally, I've tried adding a 20K pull-up (and pull-down) at Enable line.

Some more details:
- The ribbon cable between the board & the LCD is around 3-4" long.
- I also tried jumpers instead of the ribbon cable. I also tried connecting LCD directly to the main board without cables.
- The garbage pattern does not change when hitting "Reset", but DOES change when power-cycling the board. However, the first character is almost always lowercase "x". (The string I'm attempting to print is "ABCDEFGH01234567")

Any thoughts would be appreciated!

EDIT: I'm suspecting that the display itself might be faulty (unlikely, but still possible, especially with all the knock-off models)... Will try a different one just to be sure.

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deck65 - 6502 slab with screen and keyboard | ПК-88 - SBC based on KM1810VM88 (Ukrainian i8088 clone) | leo80 - simple Z80 SBC
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