Exploring the fastest production 6502 computer

[plasmo]

Well, I think I have a working 36MHz 6502 computer! DOM installed, run fine at 5V with 217mA current consumption. It will power up and load DOS/65 from DOM's system track. The software in DOM was for 14.7MHz system so the initial serial bit-bang transmitter is putting out garbage. It can be easily fixed by change couple variables in memory.

Here is a 20-second video of 36MHz 6502 hardware booting DOS/65 and run ASCIIART benchmark.
0:01 Power applied, retrieve program from DOM system track, gibberish output because the bit-bang transmitter is not set correctly for 36MHz.
0:05 started the TeraTerm macro script
0:07 transmitter was set to correct output at 36MHz clock
0:08 booted into DOS/65 and displayed directory of drive A
0:10 ran ASCIIART benchmark

This is still the CRC65 CPLD design so I need to change the memory map to maximize RAM space; I'll need to adjust software for 36MHz operation and after that I'll do pc board layout for a couple designs trying to get even more speed out of this design. I'm shooting for 40MHz operation.
Bill

Dec 18, 2022 edit: Created a homepage for this prototype that has the design information as well as additional pictures.

[Proxy]

very impressive!

40MHz would line up nicely with 800x600 SVGA, or 400x300 if you want to save on Memory (~11kB for Monochrome).
either way, having a system this fast with a display output and some form of mass storage... i wonder if GEOS would run on it (with some adjustments obviously)

[plasmo]

Thinking about the speed improvements of the overclock prototype and how it can be transferred to pc board design, I thought I would take an intermediate step and implement half of the improvements on the existing CRC65 pc board and see what improvement can be achieved. The speed improvements for existing pcb are:
* fast 10nS RAM
* fast decoding of RAM (chip select always asserted)
* buffered clock
* fast DOM interface.

The existing CRC PC board will still have DIP40 W65C02, parallel port with extra loading of address/data/control signals, and long traces between RAM, CPU, CPLD, parallel expansion, and CF interface.

So here is CRC65 rev2 PCB (a 4-layer PC board) populated with 10nS RAM with its chip select pin cut out and grounded. The DOM interface is mirrored image of CF interface, so it requires some hand-wiring to mirror the connector, but fortunately that was accomplished with few short wires. The clock line is cut and one or two 74LVC1G14 is inserted. (74LVC1G14 is an inverter, so depending on the symmetry of the clock, either inverted or non-inverted clock may achieve the most speed improvement.) The small CPLD is already 100% utilized so I have to sacrifice the I2C pins in order to have extra logic for bigger clock divider.

Here is the result: 33MHz operation is good and stable; 36MHz is occasionally achieved but seldom last more than a minute. The clock buffers, either inverting or non inverting, do not seem to make a difference, so clock buffers are not used in the end.

So intermediate PC board solution is not optimal; it is worse than a wired prototype. A dedicated PCB design is needed to get the most speed improvement.
Bill

[plasmo]

This is my idea of a fast (maybe the fastest) production 6502 computer. It is two board stack such that a PLCC W65C02 carrier board plugs into the sockets arranged as a square on the base board so to minimize connection lengths. The base board has oscillator and EPM7128S CPLD on top and a 128Kx8 fast RAM at the back. It has IDE44 interface, serial port, I2C port and run DOS/65. Except there is a problem: The 128Kx8 RAM is 400mil SOJ32. I used the wrong library of 300mil SOJ32. Oops!

Some creative wiring are needed.
Bill

[gfoot]

Interesting and creative design! Is it possible to bend out the J pins to make them reach in a bit more, or do you have something else in mind?

I am looking forward to seeing you get back into this, and seeing how far you can push it!

[plasmo]

I probably will bent out 16 J leads and solder that to one side of SMT footprint and then connect the other 16 J leads with discrete wires. I was planning to use 10nS CY7C109, but I'll use 25nS CY7C109 instead.

Lots of testing can be done without RAM, just between CPLD and 6502. So I'll do these tests first before getting the RAM patched in. In fact, I'm checking out other boards to identify potential mistakes so I can get several boards corrected on next iteration of pc boards.
Bill

[sburrow]

plasmo wrote:

Except there is a problem: The 128Kx8 RAM is 400mil SOJ32. I used the wrong library of 300mil SOJ32. Oops! Some creative wiring are needed.
Bill

If anyone can bodge that together it's you Bill.

Since these speeds are far out of spec, do you plan on testing different W65C02 chips to see 'on average' what they are actually capable of? If you get one that goes faster than others, is that... cheating?

Good updates, thanks!

Chad

[plasmo]

The various overclocking experiments I did have shown >30MHz is "touchy" and may varies from part to part as well as differences in PC board layout. To earn the bragging right of "fastest", I'm comfortable with selecting the fastest part and tune the pc board for optimal performance. However, it is important the results are repeatable. This is why it won't be "one of a kind fastest 6502" but "fastest production 6502" with all design files published to allow independent verification.
Bill

[plasmo]

This picture shows a W65C02 mounted on small carrier board plugged into the base board. I have not installed the RAM so right now this is just 6502 interacting with CPLD. In the CPLD is a bit-bang serial transmitter and a small bootstrap program that increment reg A and bit-bang reg A out to the serial port. There are no RAM so the program needs to operate with reg A, X, and Y only. I am able to run this at 36MHz and output the incrementing reg A to serial port at 115200 bps. Unfortunately this won't work at 40MHz, so I may have hit the wall at 36MHz.

Now I will bodge the RAM and see what it can do.

Bill

[plasmo]

Here is the RAM bodge. I used 25nS RAM. I bent legs on one side of SMT so they can reach the SMT pads and solder the 16 bent legs to the corresponding SMT pads; then I jumpered the other 16 pins with short wires. I added standoff so the bodged RAM is protected. It is not pretty, but it does work. This is at the nominal 14.7MHz where monitor program is loaded and RAM diagnostic ran without errors. Since it is 25nS RAM, I don't expect it to work past 30MHz.
Bill

[plasmo]

Last update for rev0 pc board:
Added the DOM disk interface. It boots DOS/65 and run BASIC compiler. It will also run at 29.5MHz. So I'm at the limit of what 25nS RAM can do. This concludes the rev0 pc board tests. I'll need to re-spin the pc board to accommodate 400mil SOJ32 RAM.
Bill

[gfoot]

Regarding clock speed limits, I have found in my current prototypes that the transition time for the address bus is forming a bottleneck. The extent of the bottleneck is partly due to a mistake in my glue logic, but the time taken still seems quite significant, e.g. 10ns before it's fully transitioned, and even more on a breadboard. This plus RAM write time plus other overheads easily adds up to 25ns or more, which matches the sort of clock speed limit you've seen so far.

In my case these pins are not heavily loaded (maybe two CMOS loads) and have fairly short trace lengths on my PCB, so I'm not sure there's much I can do about it. It'd be interesting to hear if you see the same thing - it may be different with the PLCC package, and may also be something that improves with the overvolting you've experimented with.

[plasmo]

You are right that addresses actually takes a bit of time to be valid after the falling edge of the clock. At 29.5MHz, there are only 34nS from falling edge to falling edge of clock so take away 10nS transition time and some setup time for valid data prior to sampling at falling edge, 25nS RAM really is not fast enough. It works only because the bus is lightly loaded (CPLD, RAM sharing the address bus and CPLD, RAM CF sharing the data bus) so the actual RAM access time is faster than 25nS at 5V and room temperature.
Bill

[BigEd]

> transition time for the address bus
For critical path timing, I think we used to reckon from the point the input crosses the logic threshold to the point that the output crosses the logic threshold. (Obviously, one expects these signals to reach a robust level subsequently, but that's how we measuring timing.)

(But some datasheets might give times to the 90% of eventual level.)

At this level of detail, all electronics are analogue, and it's not quite a series of discrete events involving very clean square waves!

[J64C]

Craziness! How did I miss this one?

Plasmo has always been the king of overclocking.