TTL Compatible... NOT! ( WDC )

[Dr Jefyll]

Bill, here's a bit of feedback that touches on some of your older posts in this thread. Sorry for not speaking up sooner. The thread got so busy with a multitude of folks and viewpoints that I wasn't always able to get a word in edgewise! But first, a quote from your most recent post...

BillO wrote:

But I'm really not condoning using TTL in CMOS environments.

Good to hear!

You and I are on the same page if your point is that there's a degree of compromise when TTL outputs drive CMOS inputs (other than those such as 'HCT series inputs). Trouble may result... Or not, depending on your luck and whether your design also includes other compromises (compromises that increase ground and Vcc noise, for example).

BillO wrote:

What I'm really trying to say is those CMOS RAM, ROM and PLD devices we use (and only get TTL load specs for) will do fine in CMOS environments and we need to stop taking those TTL environment specs so seriously because that is just no longer the reality.

upthread, BillO wrote:

4) Basically 100% of CMOS devices have the nice, simple stacked MOSFET outputs we are all familiar with. They all work the same.

Two more quotes. And although the first has a grain of truth in it, I'm forced to straight out disagree with the second. You seem to imply that the outputs of all CMOS devices can be expected to produce rail-to-rail output voltage swings. I wish that were true -- and it used to be true -- but (as the saying goes), they don't make 'em like they used to!

It's not all across the board. For example, 74AC Series logic and similar products do still feature rail-to-rail output voltage swings (and the specs reflect this). But modern 5 volt LSI devices such as RAMs and CPLDs typically do not. I have a couple of theories on why that might be, but I'm not an expert and I'll save those details for another time. But for economic reasons the industry is tending toward smaller process geometries, and with those come lower operating voltages.

Again and again in this thread we're asking ourselves how conservative the specs are.

• We know TTL chips typically exceed their output specs, and that one can (with a compromise, as noted) feed a TTL output to a CMOS input.
• you seem to be saying that we're safe in assuming that CMOS chips exceed the TTL spec even more, based on their simple stacked MOSFET outputs.

It's a shame that data sheets typically say so little about output characteristics. But, as an exception to the rule, here's a graph that's far more revealing:

This CPLD is described by its manufacturer as CMOS, and internally it probably is. But its output stage does not behave like the simple stacked MOSFET outputs we are familiar with. Specifically, Vo fails to even approach the 5V rail... even when the output current (ie, load) is zero. I don't see how this graph can be reconciled with your suggestion (in this post) that the output, when in its high state, can be modeled as a simple resistor to Vcc.

This is not CMOS like we had in the old days. So, correct me please if I've mistaken your point, but if you're saying that any CMOS chip is automatically OK voltage-level-wise to drive other CMOS, I can't agree. There's definitely been a change since you & I entered the biz. These new-fangled, so-called "CMOS" outputs on 5V-powered LSI devices do still manage to produce levels that conform to TTL spec. But we can't assume that they exceed the spec by a greater margin simply because of the device's CMOS-ness!

-- Jeff

[BillO]

It interesting to note though that those same parts will go rail to rail at 3.3V. I'm not sure what is going on vis-a-vis the VccIO circuitry but I agree, it cannot be standard CMOS output technology. In any case I wasn't referring to those sorts of parts at all. Things more like 27C series EPROMs or GALs or 64C series RAM and the like. CMOS chips from the past that get a "that's not spec'd to work in CMOS stuff" comment every time someone mentions them.

[BigDumbDinosaur]

BillO wrote:

Things more like 27C series EPROMs or GALs or 64C series RAM and the like. CMOS chips from the past that get a "that's not spec'd to work in CMOS stuff" comment every time someone mentions them.

Each of my POC units has used RAM and ROM with TTL-level outputs. The theoretical maximum VOH for these devices is ~3.4 volts with a vanishingly small load. Using my clock single-stepper to stop the 65C816 in the Ø2 high phase, I was able to measure the output voltages of both RAM and ROM with a DVM. Both were around 3.3 volts.

Jeff had measured the "trip" voltages on some WDC MPUs and reported that the transition from a logic 0 to a logic 1 occurred around 2.6 volts. That explains why the RAM and ROM with their TTL-level outputs work with an MPU with CMOS input specs—the MPU was seeing a solid logic 1. However, I don't think that behavior will be reliable in cases where parasitic capacitance is significant. The rise from zero to the guaranteed 2.4 volt VOH will certainly be plenty quick, but the curve will rapidly flatten out above that as the parasitic capacitance is charging.

Dr Jefyll wrote:

This is not CMOS like we had in the old days. So, correct me please if I've mistaken your point, but if you're saying that any CMOS chip is automatically OK voltage-level-wise to drive other CMOS, I can't agree.

Yep! The only VOH spec that is guaranteed for devices with TTL outputs is 2.4 volts under maximum loading, which is well below a solid CMOS logic 1. Fortunately, CMOS devices don't impose any significant loading except during state transitions. So we can expect VOH to be better than that.

BTW, I'm in the process of preparing and testing the CPLD (Microchip ATF1504AS) for POC V2.0. The ATF150*AS series has TTL-level outputs. Just for grins, I sampled some of the outputs when high, again using a DVM and while the CPLD was in my Atmel test rig, which imposes no loading on the CPLD—VCC is 5 volts. All outputs are right around 3.3 volts. V2.0's design includes pull-up resistors on CPLD outputs. These are a fairly low resistance (680Ω) to help boost the CPLD into "CMOS orbit" when it emits a logic 1.

As for the RAM and ROM, I decided to add a 74ACT245 bus transceiver to V2.0 to act as a level converter, as well as to isolate the 816 during Ø2 low. As Jeff has noted in his to-scale timing diagram, there is a small window of opportunity for contention to occur as the 816 "turns around" the data bus when Ø2 goes high. Due to the slight lag from when the clock rises until the ACT245 comes out of high-Z, that window should be closed.

As the ophthalmologist said, we'll see.

[kernelthread]

Looks a bit like 2 or 3 diodes and a 25 ohm resistor all in series. But if you run it with VCCIO=3.3V somehow the diodes are bypassed. For some reason they've gone out of their way to limit the positive voltage excursions when running on 5V. I wonder if the idea is you can connect the outputs to 3.3V logic? VccIO can be 5V or 3.3V, but VccINT is always 5V. It would be more understandable if the guts ran at a lower voltage than the I/O.

[BigDumbDinosaur]

kernelthread wrote:

Looks a bit like 2 or 3 diodes and a 25 ohm resistor all in series. But if you run it with VCCIO=3.3V somehow the diodes are bypassed. For some reason they've gone out of their way to limit the positive voltage excursions when running on 5V. I wonder if the idea is you can connect the outputs to 3.3V logic? VccIO can be 5V or 3.3V, but VccINT is always 5V. It would be more understandable if the guts ran at a lower voltage than the I/O.

I've not seen what I would consider to be a satisfactory explanation of how it's done, or why. It could be there is some sort of LDO regulator involved so VCCIO is internally 3.3 volts open circuit, no matter the external VCC.

[BillO]

BigDumbDinosaur wrote:

The theoretical maximum VOH for these devices is ~3.4 volts with a vanishingly small load.

This is my entire point BDD. The spec sheets for these devices have a "theoretical" (CYA) max of ~3.4V for a load of 400uA which is 10 TTL loads. In today's world that is NOT vanishingly small. It is unreasonably huge. In my other thread I've already shown even LS TTL will meet CMOS input voltage levels, albeit marginally, with a 6 CMOS input load which is pretty typical for the kind of machine we folks produce these days. But let's not dwell on LS TTL, none of us should be using that to drive CMOS CPU buses. When I can get the time I will be doing similar tests on these devices with those "theoretical" 3.4Voh specs.

I expect there will be no issues. I could be wrong, so stay tuned.

[plasmo]

Here are a couple pictures from page 17 of ATF1508AS data sheet that are of interest to this topic.
Bill

[plasmo]

Voh and Vol characteristics of TI high speed CMOS (HC) logic family. Page 873 of 1988 TI’s high speed CMOS data book.
Bill

[kernelthread]

The sink current graph for the ATF1508AS and the 74HC are quite similar in shape - pretty linear to 1V output, rolling over to 2V, then only a small increase in current to 5V. But the source current graph is completely different - apart from never sourcing >4V, the 1508 output is much more linear at high currents and low output voltages. It looks like the output pull-down element is a standard N channel mosfet for both the 1508 and 74HC, but whereas the pull-up element of the 74HC is a standard p-channel mosfet, the 1508 has something more complicated.