Bill, here's a bit of feedback that touches on some of your older posts in this thread. Sorry for not speaking up sooner. The thread got so busy with a multitude of folks and viewpoints that I wasn't always able to get a word in edgewise! But first, a quote from your most recent post...
BillO wrote:
But I'm really not condoning using TTL in CMOS environments.
Good to hear!
You and I are on the same page if your point is that there's a degree of compromise when TTL outputs drive CMOS inputs (other than those such as 'HC
T series inputs). Trouble may result... Or not, depending on your luck
and whether your design also includes other compromises (compromises that increase ground and Vcc noise, for example).
BillO wrote:
What I'm really trying to say is those CMOS RAM, ROM and PLD devices we use (and only get TTL load specs for) will do fine in CMOS environments and we need to stop taking those TTL environment specs so seriously because that is just no longer the reality.
upthread, BillO wrote:
4) Basically 100% of CMOS devices have the nice, simple stacked MOSFET outputs we are all familiar with. They all work the same.
Two more quotes. And although the first has a grain of truth in it, I'm forced to straight out disagree with the second. You seem to imply that the outputs of all CMOS devices can be expected to produce rail-to-rail output voltage swings. I wish that were true -- and it
used to be true -- but (as the saying goes), they don't make 'em like they used to!
It's not all across the board. For example, 74AC Series logic and similar products do still feature rail-to-rail output voltage swings (and the specs reflect this). But modern 5 volt LSI devices such as RAMs and CPLDs typically do not. I have a couple of theories on why that might be, but I'm not an expert and I'll save those details for another time. But for economic reasons the industry is tending toward smaller process geometries, and with those come lower operating voltages.
Again and again in this thread we're asking ourselves how conservative the specs are. - We know TTL chips typically exceed their output specs, and that one can (with a compromise, as noted) feed a TTL output to a CMOS input.
- you seem to be saying that we're safe in assuming that CMOS chips exceed the TTL spec even more, based on their simple stacked MOSFET outputs.
It's a shame that data sheets typically say so little about output characteristics. But, as an exception to the rule, here's a graph that's far more revealing:
Attachment:
Max7000 output drive characteristics.png [ 26.31 KiB | Viewed 3154 times ]
This CPLD is described by its manufacturer as CMOS, and internally it probably is. But its
output stage does
not behave like the simple stacked MOSFET outputs we are familiar with. Specifically, Vo fails to even approach the 5V rail... even when the output current (ie, load) is zero. I don't see how this graph can be reconciled with your suggestion (in
this post) that the output, when in its high state, can be modeled as a simple resistor to Vcc.
This is not CMOS like we had in the old days. So, correct me please if I've mistaken your point, but if you're saying that any CMOS chip is automatically OK voltage-level-wise to drive other CMOS, I can't agree. There's definitely been a change since you & I entered the biz. These new-fangled, so-called "CMOS" outputs on 5V-powered LSI devices do still manage to produce levels that conform to TTL spec. But we can't assume that they exceed the spec by a greater margin simply because of the device's CMOS-ness!
-- Jeff
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