Yeah, but the point of it is to illustrate that the write pulse is guaranteed to be set before the address setup (as per the data sheets).

If in practice, it happens the other way around, then great, we got lucky! I prefer to alway work for worse case every time.

I think you might miss part of hoglet's point there...

The trailing edge of Write, which is caused by Phi2's falling edge, and lags it by an indeterminate amount, is a grey area. As it coincides with the grey area of the address bus, there's a double unknown: you don't know if you're writing, and you don't know where to.

On paper and whiteboards, I like sometimes to put a wibbly arrow from the edge which causes something to the event which it causes. It's more difficult to do this in a graphic. But I find it really helps to show why things happen in the order that they do happen. Failing the wibbly arrow, it can help to shift things slightly: things caused by something can be shown as happening very slightly later.

So, that's a couple of suggestions for an improvement to a diagram which is already a useful diagram: thanks for drawing and sharing!

Indeed -- like this:
-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Jeff, what do you use to create your timing diagrams?

_________________
Bill

It looks like WaveDrom, which is an online editor:
https://wavedrom.com/editor.html

I don't know how J64C created the diagram. Could've been WaveDrom, as hoglet suggested. I merely edited the bitmap that was already there, using Paint Shop Pro (which is equivalent to PhotoShop).

So, I'm working at the pixel level. PSP doesn't "understand" timing diagrams. But the program is excellent, and I've had enough practice that I've gotten pretty speedy.

And I can edit almost anything. Nearly every image I post on this forum comes from PSP, including alterations to the work of others, and original images of my own (including my animated avatar).

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

From what I understand the VIA IC's don't require write qualification as they 'know' about how the W65C02's work. Is this correct?

What happens if you do still use the qualified write circuit on a VIA? Will it still function correctly?

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Interesting! Thank you so much for the advice!

I can't be sure (because I did it over 30 years ago) but I think I got away with un-qualified writes on a small breadboard project with a 'c802, PIA, EPROM and SRAM. ISTR running it at 1 MHz and 2 MHz without incident. Maybe it was dumb luck?

_________________
Got a kilobyte lying fallow in your 65xx's memory map? Sprinkle some VTL02C on it and see how it grows on you!

Mike B. (about me) (learning how to github)

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

The thing about un-qualified writes is, you might not be aware you have a problem. By intentionally writing to address 1234, for example, you might also unintentionally alter memory at some other address(es).

If the address(es) affected happen to be unused then the problem may go unnoticed.

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

I learned this the hard way a few years back (with the help of the great people here). In my early years I seemed to get away with all sorts of nonsense. However, when I tried that with updated chips and memory .. well they just did not seem to have the sense of humor the stuff available back in circa 1979 did. Now I qualify both read and write. Makes for less head banging.

The 65XX chips do their own read and/or write qualifying. They expect an unaltered R/W along with phi2 to manage the timing. Supplying a pre-qualified R/W signal might not leave them enough time to figure things out. That old accumulated propagation delay thing..

_________________
Bill

The C64 is a tricky beast. The CPU only gets the bus on the high clock and the VIC2 chip gets it on the lock phase (forcing the CPU to high Z itself). Maybe it was something along those lines that influenced your design at the time.

Oh my goodness, yes. I made it through my early "invincible" twenties with the loss of only a few hundred thousand brain cells, but luck was definitely on my side, because things could have been much, much worse.

_________________
Got a kilobyte lying fallow in your 65xx's memory map? Sprinkle some VTL02C on it and see how it grows on you!

Mike B. (about me) (learning how to github)