Techniques for reliable high-speed digital circuits

[GARTHWILSON]

BillO wrote:

Here is a good video on this subject:

https://www.youtube.com/watch?v=STCGzanAyR0

Gets into a lot of detail we may not need in the 6502 world, but better stuff to have in your brain than the latest episode of The Gilmore Girls. Is that still a thing? I remember getting kicked out of the TV room so my better half and our daughter could watch that show.

That's a good one. At 17:10 he says some board manufacturers will tell you to avoid sharp inside corners because acid can collect there, and said if they say that, get another manufacturer. I don't know about "collecting," but when I used to make my own boards, I remember it was really hard to totally wash the etchant out of such corners, and corrosion would happen there in subsequent months and years, which is why I try to keep the angles more open now, not anything about signal reflections. We did deal with the shape of the corners when I worked in applications engineering at a company that made RF power transistors mostly for military radars and communications, but that was with wider traces and GHz frequencies like Bill Herd said. Dr. Howard Johnson had a short article called, "Who's Afraid Of the Big, Bad Bend?" [Edit: Found it. https://web.archive.org/web/20110910025 ... adbend.htm ]

Although we do need to be conscious of transmission-line phenomena and what happens in the ground plane in our 65xx PCBs (something he did briefly touch on), the high-frequency behavior of a trace corner is, as he says, not a concern at frequencies we're dealing with (where the highest of our significant frequency components are under a half a GHz).

Edit: This was referenced in the topic "All about inductance: article and video by Bil Herd," with additional links to relevant topics here on the forum.

[BillO]

Another great video by Bill Herd on this subject:

https://www.youtube.com/watch?v=OQm0aBw_ep8

[Tor]

marcelk (from the Gigatron design team) posted a link to an informative Dave Jones video (EEVblog #1176), over on the Gigatron forum. Dave Jones has built two Gigatrons, one is the 'standard' two-layer board, another is a four-layer board, and what's unique is that the two boards are exactly the same as far as the signal traces are concerned. You have to look closely to notice that one is a four-layer board. Then he measures near field emissions of the two boards. Very interesting.

https://www.youtube.com/watch?v=crs_QLuUTyQ

(The gigatron forum posting I took this from: https://forum.gigatron.io/viewtopic.php?f=4&t=85)

[BigEd]

Thanks! One takeaway is that you can build a mass-market product clocked a little over 6MHz with a two layer board. (I really want it to be true, and for every beginner to know, that four layers and ground planes are not necessary for modest projects!)

[Arlet]

In the 2nd part of the video Dave is showing the traces and the path of the return current. You can see that the ground "planes" don't actually extend between 2 neighboring pins of the DIP packages, even though you can see traces fit through there. If a trace fits, then the ground pour should also fit.

A simple way to improve this particular 2 layer design is to adjust the clearance parameter on the pours so that the ground planes will actually go between the pins. This is simple and free, and will probably get you a very decent improvement.

The defaults provided by the PCB design program may be too conservative for the capabilities of the PCB fab, so I would recommend first picking a manufacturer, find out what they offer in terms of clearance, track width, and drill sizes, and then use those settings in the PCB design program. Some manufacturers actually provide ready-made design rule files that can be imported in the program.

In addition to checking clearance and track width, it's worth it to take a good look at the pad size and drill diameter. Maybe the default drill and pad can be reduced a bit to fit more between. As an example, here's a screenshot of a 2 layer board (the 6502 sandbox) I did. It was designed for Eurocircuit design rules, as offered in their basic (lowest cost) option. As you can see, there's room for 3 wires between 2 pins @ 100 mil spacing, or, in this case, a single wire plus ground on either side.

Just a few hours of prep work here can save a lot of effort and performance later.

[mvk]

Arlet wrote:

In the 2nd part of the video Dave is showing the traces and the path of the return current. You can see that the ground "planes" don't actually extend between 2 neighboring pins of the DIP packages, even though you can see traces fit through there. If a trace fits, then the ground pour should also fit.

A simple way to improve this particular 2 layer design is to adjust the clearance parameter on the pours so that the ground planes will actually go between the pins. This is simple and free, and will probably get you a very decent improvement.

Well-spotted, dank je wel! We helped the pour algorithm a bit by manually running some dummy ground trace between pins. In a next spin I'll tweak with these settings, it makes so much more sense. I don't know if it will do much. There's a reason home computers came in faraday cages. Dave also makes a good point about the caps. I think at that point we can simply do a 4-layer board, but keep the 2-layer retro"look" with the pours as-is.

BigEd wrote:

Thanks! One takeaway is that you can build a mass-market product clocked a little over 6MHz with a two layer board. (I really want it to be true, and for every beginner to know, that four layers and ground planes are not necessary for modest projects!)

Trust me, TTL computer DIY soldering kits are not a mass market thing.

[enso]

Question: if PCB traces require a ground-plane for a clean return path of high-frequency signals, and ribbon cables require every other strand to be grounded for the same reason, why do wire-wrapped circuits work as well as they do?

PS. I used a 2-layer board in OberonStation, an FPGA-based Oberon workstation. It ran a 25-MHz CPU (60MHz crystal) with external memory and IO with no apparent problems...https://web.archive.org/web/20180102133 ... x10.mx:80/

[GARTHWILSON]

enso wrote:

Question: if PCB traces require a ground-plane for a clean return path of high-frequency signals, and ribbon cables require every other strand to be grounded for the same reason, why do wire-wrapped circuits work as well as they do?

WW allows you to put the sockets shoulder to shoulder with no space between them, for maximum board density for the IC package size, making for the shortest possible connections. Still, the waveforms on my workbench computer with 4MHz parts (running at 5MHz, 70% of the speed where the first problems show up), 55ns SRAM, 70ns EPROM, and 74AC logic look pretty frightening on the oscilloscope! I'm sure it's working not far from the raggedy edge. I didn't know as much about this stuff when I built it. I'll definitely use perfboard with a ground plane the next time, or even planes on both sides so the top can be Vcc (or just go for a PCB).


I understand the Cray-1 had loads of WW wire and ran at 80MHz, but each wire was in a twisted pair with its ground-return wire.

Quote:

PS. I used a 2-layer board in OberonStation, an FPGA-based Oberon workstation. It ran a 25-MHz CPU (60MHz crystal) with external memory and IO with no apparent problems...https://web.archive.org/web/20180102133 ... x10.mx:80/

Its small size worked to your advantage. The longest connections are pretty short. What are the rise times? The clock line is the most critical. It helps if that doesn't have to go as far as the address and data lines for memory or I/O.

But with 74HC-range rise times, you can get away with murder in your construction. 74AC, not so much.

[BigEd]

enso wrote:

Question: if PCB traces require a ground-plane for a clean return path of high-frequency signals, and ribbon cables require every other strand to be grounded for the same reason, why do wire-wrapped circuits work as well as they do?

Because the risks are over-stated, and the need for reliability of a hobby or prototype system is completely different from the need of a mass production or life-critical system. The latter may well 'require' good attention to signal integrity, the former may only 'benefit from' such attention.

Edit: that said, if a beginner is trying to debug a design, it's helpful if they haven't built it in a way which is inherently unreliable.

[BigDumbDinosaur]

Further to the design of a good printed circuit board, here is a link to a trace width calculator that may be useful.

[GARTHWILSON]

BigDumbDinosaur wrote:

Further to the design of a good printed circuit board, here is a link to a trace width calculator that may be useful.

Note that that one is for DC current-carrying capability of a trace, which is a good link to have since people often think they need power-supply traces much wider than they really do.

Hmmm...There seems to be something wrong with that page. It's telling me that a .006" trace of 1oz copper, 4" long, has 329Ω! The reality is nowhere near that much. Oh, I see the problem. That's milliohms (ie, 0.329Ω), but it's labeled wrong. I got that from https://www.eeweb.com/tools/trace-resistance . They have a similar page about max current that was giving me a number more than twice that high, so I calculated it myself, and the 329milliohm number is the correct one.

For AC performance, if transition times are fast enough and line lengths long enough for transmission-line characteristic impedance to matter, there's an online calculator at https://www.eeweb.com/tools/microstrip-impedance .

For the few who aren't afraid of some heavy-ish math, Dr. Howard Johnson addresses losses and other characteristics due to skin effect in articles linked here. Otherwise, don't worry about it. Skin depth of copper at 100MHz is about 250 microinches. Standard 1oz copper is .0014" thick, so the resistance of a narrow trace at 74AC edge speeds should be somewhere around five times what the DC resistance is; but five times the third-of-an-ohm number above is still piddly, for digital signal lines! Also, where there's no power plane, power-supply lines will be bypassed to ground right near each IC's VDD pin, so skin effect won't really matter there either. [Edit: Also, wire size has very little effect on inductance. In a wire, multiplying the diameter by ten (.010" WW wire to .100" super-fat bus wire) and the cross-sectional area by 100 won't even cut the inductance in half. That's from https://www.eeweb.com/tools/wire-inductance . That's a huge difference it wire size with very little difference in inductance. I don't have a resource to calculate the difference for flat traces, but I suspect it's the same story, meaning that making your power traces extra wide won't have much effect on inductance there either. Edit, 2/19/22: There's a trace inductance calculator, actually for flat wire that's not against a ground plane, here. Multiplying the width of a 2"-long trace on 1oz copper, from .010" to .050", ie, multiplying the width by five, the reduction in inductance is not even 25%. So don't worry about making traces wider to cut inductance.]

[BigDumbDinosaur]

GARTHWILSON wrote:

For the few who aren't afraid of some heavy-ish math, Dr. Howard Johnson addresses losses and other characteristics due to skin effect in articles linked here. Otherwise, don't worry about it. Skin depth of copper at 100MHz is about 250 microinches. Standard 1oz copper is .0014" thick, so the resistance of a narrow trace at 74AC edge speeds should be somewhere around five times what the DC resistance is; but five times the third-of-an-ohm number above is still piddly, for digital signal lines! Also, where there's no power plane, power-supply lines will be bypassed to ground right near each IC's VDD pin, so skin effect won't really matter there either.

POC V1.1 is running on my desk at 14.1 MHz and when scoped, looks pretty clean. Signal traces are 6 mil and the board is four layers, with 1 ounce copper. The four-layer construction shows its value in the general quietness of the unit and the absence of ground bounce.

For most of us, transmission line effects should not be a problem—assuming construction is with tight wire-wrap or on a PCB with a reasonable layout. Many of our gadgets don't run all that fast and even the ones that do run fast aren't running fast enough for signal propagation time and all that that entails to cause any grief. More likely, trouble will arise from very fast signal edges, which are characteristic of the high-speed logic families.

Nevertheless, knowing some transmission line theory can help with physical design. In that regard, Dr. Johnson is considered an expert among experts and I highly recommend his material. Yes, it's technical and some of it may be math-intensive, but his expositions are written in a lucid style and are understandable. In other words, you won't need an advanced degree to learn something.

[Ruud]

I am new to creating PCBs and yesterday I started reading this thread. A hole new world opened but at the end I was really confused. There was only one light in the dark for me: I checked various XT clone turbo boards and many of them were just two layers, no plane filling and no terminators. And they work at 8 MHz. So there is still hope for my designs.

What I could use is document explaining some basic rules or guide lines for dummies:
- How wide should signal traces be? Is wider better or even worse? Other basic rules like no sharp angles?
- Is there a maximum length, or better, are there rules regarding length?
- When to use termination? Should it be 220/330 or can a bunch of 10 K resistors be OK as well? (found them on various PC motherboards as terminators)
- When is four layers a must?
- If using two layers, what should taken care of / where should be paid extra attention to?
- If using two layers, when should copper filling be applied? Or maybe when not? (Is this filling between the traces called the ground plane?)
- Are there rules where capacitors should be placed? ( I now put them if there is place available and near the IC)

If you can answer only a few of the questions, I don't mind to collect all answers and to create this document for the benefit of all.

[BigEd]

I think one reason this thread might come across as shocking is that it includes all sorts of advice, ranging from 'this is absolutely necessary for anything to work' to 'this is appropriately conservative for volume production.'

Commonly enough you'll also see phrases like 'as close as possible' or 'as short as possible' which again don't quite mean what they seem to: 'closer is better' and 'shorter is better' might be improvements.

The key word, I think, is 'reliable' - and there are various levels of acceptable reliability. Again, a one-off build which you're prepared to investigate and debug is one thing, a design for volume production with high yield, reliable operation in the field, and negligible customer returns, is another.

But I think it's true that there's some truth behind each piece of advice: what's difficult is the sense of judgement, as to which is most important and how much difference it makes.

It is of course very much harder to say how much each millimetre of distance between an IC and its bypass capacitor is worth, than to say the capacitor should be as close as possible. It's probably true that it's less critical if the IC doesn't draw so much peak current, or is of a family which has better voltage margins, or if the power distribution is low resistance and low inductance.

It would be good to have rules of thumb, relating to choice of logic family, maximum speed, number of strobes, clocks, and pulses, style of power distribution. The thing is, these various degrees of freedom interact.

Sorry, this is not an immediately helpful response!

[GARTHWILSON]

Ruud wrote:

I am new to creating PCBs and yesterday I started reading this thread. A hole new world opened but at the end I was really confused. There was only one light in the dark for me: I checked various XT clone turbo boards and many of them were just two layers, no plane filling and no terminators. And they work at 8 MHz. So there is still hope for my designs.

Are you sure there were no internal plane layers? I don't think I've seen XT-class PCs with only two layers. 8MHz doesn't mean the same thing as 8MHz in a 65c02 system though, right? The big deal is the edge rates though, not the MHz, which is why 74HC is much more forgiving than 74AC, even at the same number of MHz. (74AC's propagation delays will be only one-half to one-third as longs as 74HC's though.)

Quote:

What I could use is document explaining some basic rules or guide lines for dummies:

I think all the answers are in the preceding pages, or at least in the linked articles of Dr. Johnson's; but I know it's a lot to get through.

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- How wide should signal traces be?

Keeping the trace length short is the way to minimize transmission-line problems as well as the need for terminations, and you can do that by putting the parts close together so you can hold the board size down, which means making the traces quite narrow. All PCB houses now can do down to .006" trace & space without charging extra, some maybe even a little narrower.

A lot of people think you need the power and ground traces to be really wide. The skin effect is minimal though in our stuff, and even tripling the width has very little effect on inductance, and an .008" trace on 1oz copper can carry half an amp. So don't worry about it.

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Is wider better or even worse?

Width affects the characteristic impedance of transmission lines; but without a ground plane, you won't have transmission lines anyway; and if you did, the impedances that our stuff would want is pretty high compared to what you'd get with normal traces, meaning wider is not better.

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Other basic rules like no sharp angles?

Sharp angles won't matter for the performance. I keep angles exiting pads to no sharper than 90°, and trace corners 45°; but that's for reliability, and was to address a manufacturing problem that might not exist in anymore, that of washing the etchant out really well so there's none left in the nooks and corrosion doesn't set in.

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- Is there a maximum length, or better, are there rules regarding length?

Answer is at viewtopic.php?p=33837#p33837 . Maximum length and the need for terminations are related to each other and to edge rates (not MHz).

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- When to use termination? Should it be 220/330 or can a bunch of 10 K resistors be OK as well? (found them on various PC motherboards as terminators)

Resistive terminations won't do any good if they don't match the characteristic impedance of the transmission line. Hopefully you can make the design compact enough that you don't need to worry about that. If you did need to worry about it, then you'd have to control the transmission-line impedance with not only the width but also the distance to the ground plane. Diode terminations work better when you don't have control of the transmission-line impedances; but there are very few diodes that are fast enough to do any good.

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- When is four layers a must?

If you can get your design on something like 15cm square or smaller, you can probably go without, unless you wanted to sell it and had to get the product certified for how much electrical noise it radiates. It will radiate a lot of electrical noise without at least a ground plane implemented correctly.

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- If using two layers, what should taken care of / where should be paid extra attention to?

The main thing will be holding the impedance of the power and ground connections between ICs. Do not run power down one side of the board and ground down the other, with fingers that reach down the rows of ICs! Doing that requires the ground return current for a signal line to go clear down to the end of the row and up the next row, which gives the connection a lot of inductance, and you'll get a lot of ground bounce. Instead, make overlapping power and ground grids, like a quadrille mesh. The ground connection and power connection from one IC to the next should be as short as practical.

Of all the signals, the clock is the most important to keep clean. You can get away with more ringing on things like address and data buses without crashing the system.

If you have connectors with lots of pins, do not put all the power and ground pins at the ends. Distribute them evenly down the length of the connector.

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- If using two layers, when should copper filling be applied? Or maybe when not? (Is this filling between the traces called the ground plane?)

"Copper pours" (or fills) do not qualify as a ground plane. Not at all. I give a diagram at viewtopic.php?p=55094#p55094 showing what goes on, with a mechanical analogy. A signal's ground return current must run very close to the signal line, without interruptions. Copper pours will have interruptions. It is explained there. There is a way to use pours to supplement real planes; but if they're not done correctly, they can actually make things worse, according to experts in the field like Rick Hartley, Eric Bogatin, and Suzie Web whose lectures you can see on Altium's YouTube channel.

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- Are there rules where capacitors should be placed? ( I now put them if there is place available and near the IC)

Make the shortest connection you can from the IC's ground pin, through the capacitor, and up to the Vcc pin. If you use thru-hole capacitors, solder them all the way down to the board with almost zero lead length. There's a relevant post here. Whether the capacitor is closest to the ground pin or the power pin does not really matter if you only have two layers.

This is important stuff, but it's awfully hard to model it so as to give numerical rules. Even many experts, based on their experience, disagree on things like for example how long traces can be for a given edge rate before you need terminations. So much of this falls under that nebulous term "good engineering practice." Just get all the information you can and exercise "good engineering practice," and you'll probably do fine. We do occasionally get people here posting about problems they can't figure out even though their connections are all per the schematic. The problems are nearly always on solderless breadboards which violate every principle in the book.