EDIT: Bitwise posted while I was posting this so sorry if I have duplicated his efforts. Must read his post and see if he came up with something clever! - Yep, he did :D

The easy way to handle the packing is to have three seperate encoding routines, one handles 1 byte, one handles 2 bytes and one ...

Just remember

Things like the colour burst and the chroma sub-carrier do not need to be sine waves. Square waves would have their harmonics stripped off by the filters in the TV set anyway and so would have no significant effect on the picture.

If you want to switch the CPU clock speed cleanly, have a look at this article: http://6502.org/mini-projects/clock-swi ... ching.html

It shows how to switch between two clock speeds without creating glitches.

This fragment is from the Acorn Teletext VDU manual. It determines if an Op-Code is a single byte, 2-byte or 3-byte instruction. It only works for the NMOS instruction set and doesn't give any details of the addressing mode but somebody might find it useful.



Enter with the Op-Code in A

CMP #$20 ...

Do any of your scopes have an X output (Usually, older scopes had this.)

You could then feed it to the X input of the others and they would all run to the same timebase. (assuming the others have an X input. Modern scopes make you sacrifice a Y channel for an X input!)

It is better to disable a battery-backed chip by holding CS high. Not because this is a superior write-protect, but with CS held high, some ICs draw less power than they do with CS low and WE and OE high. This obviously equates to a longer battery life.

As far as the dedicated battery-backup ICs go ...

For suspending interrupts, instead of SEI, you can tell the IC not to interrupt until further notice, or mask NMIs in hardware with a separate gate, maybe an AND gate.

To DISABLE interrupts, you would need an OR gate or a NAND gate, as you want to hold the output high when interrupts are disabled ...

If you're using a 5V supply, consider using NiMH instead of lithium batteries. Although the energy density is not as good, charging is simple and a string of 4 NiMH calls gives 4.8V - This is within 5% of 5V so no regulator is needed at all.

Check out the data sheet. The response falls off below 2kHz. Any sound played through this is going to sound very tinny and lacking not just in bass but mid-range as well. Unless you are really strapped for space, I suggest you go for a conventional speaker of 2 to 3 inches diameter - it will sound ...

Whilst looking through some old magazines (1968 to be exact), I found a cure for the turn-on thump created by IC amplifiers. You only had to look upthread , Paul! :mrgreen:

You've described it nicely, though. To cure the problem, connect two capacitors in series across the power supply [ as in (b ...

Whilst looking through some old magazines (1968 to be exact), I found a cure for the turn-on thump created by IC amplifiers.

The thump is caused by the speaker coupling capacitor charging through the speaker.

To cure the problem, connect two capacitors in series across the power supply. Each ...

...someone was using the line voltage (120VAC) as a 60Hz reference for a PIC16 microcontroller, using a huge resistance in series (maybe 10M or 22M—I can't remember) to hold the current down to something that the input protection diodes could handle continually with no damage.
Talk about living ...

There is another reason why you must always connect all the inputs of a CMOS logic IC.

With their very high input impedance, it doesn't take much charge to build up sufficient voltage to overcome the insulating layer between the MOSFET gates and the channels. Stray static is sufficient. When this ...

As Dr Jefyll and BDD have already said, although the internal logic diagram shows a chain of five gates, this doesn't mean the 74HC139 has the propagation delay of five gates. The typical propagation delay of a 74HC139 at 5V is 11ns, that of a 74HC00 at 5V is 7ns. This gives a total propagation ...

The 4011 is far too slow. The BDIR and BC1 pulses need to end just a few tens of nanoseconds after CLK2 goes low, before the data on the data bus becomes invalid. After the delays introduced by the 4011, the data on the data bus will be invalid long before the BDIR and BC1 pulses end and the AY-3 ...