Write Protect and battery backup Qs

[richardc64]

Which is the better way to Write Protect memory? To prevent /WE (and /OE of course,) from going low when R/W and the RAMs' /CS =0, or by preventing /CS from going low altogether?

Is either way vulnerable to glitches I haven't anticipated?

Two-part 2nd Q: In the past I have battery-backed SRAM with a 74HC__ gate powered by +5v and the battery voltage in the /CS path, and that has worked well. I am wondering, though, if it makes any difference if unused other gates in the package are terminated high or low? Does it make any difference if other gates in the package ARE used elsewhere in the circuitry? Past experience tells me "No", so consider this question me double-checking with people who know more than I do.

I am opposed to using any fancy Maxim IC for battery backup.

Thanks,
Richard

[GARTHWILSON]

Here's a relevant post: viewtopic.php?p=32004#p32004

I made a circuit 30 years ago at work that had an 8Kx8 SRAM and a real-time clock, battery-backed. These both had two chip-select inputs; so when the power was going down, the circuit set one of the chip selects false, and set it true again after the power came back up and was stable. The parts were all cheap; but it took a lot of them compared to the Maxim IC you don't want to use. If a chip-select input is false, the write-enable and output-enable inputs are "don't care"s.

Don't leave any CMOS inputs unconnected though. It normally doesn't matter if you tie them high or low. I'm not sure what you're asking in the rest of the question though.

[Dr Jefyll]

richardc64 wrote:

I am wondering, though, if it makes any difference if unused other gates in the package are terminated high or low? Does it make any difference if other gates in the package ARE used elsewhere in the circuitry?

If outputs from gates in the battery-powered IC drive other circuitry that's NOT battery-powered then you probably need to ensure those outputs go low* during battery operation. (Is that what the second sentence is asking?) I'm assuming battery negative always remains connected to logic ground (unlike less common schemes where battery positive always remains connected to Vcc. For those, replace the word low* with high, and infer similar changes in the following.) The problem is a high output can end up powering the other circuitry. Inputs on logic IC's generally have an internal protection diode connecting the input to Vcc (and another to Gnd), and the diode provides a path from the input to Vcc anytime Vcc has a lower voltage than the input. However, some of the newer logic families (I think 74AHC is one) omit the diode to Vcc. In that case it's OK if its input gets driven high while the chip is powered down.

BTW I'm with Garth when it comes to roll-your-own circuits for detecting out-of-spec Vcc (ie, power fail). Been there done that, and nowadays I would use the new-fangled IC and be heartily grateful for it!

[PaulF]

It is better to disable a battery-backed chip by holding CS high. Not because this is a superior write-protect, but with CS held high, some ICs draw less power than they do with CS low and WE and OE high. This obviously equates to a longer battery life.

As far as the dedicated battery-backup ICs go, they are much easier to use than trying to implement your own design. Most of them handle switching between the two supplies without glitches and provide an output that can be used to control your write-protect logic. I would strongly recomend you use one of these ICs than trying to design your own circuit - it's just so much easier.

[Windfall]

<overstate> Battery backup is the spawn of the devil. </overstate> They need changing, get whiskers and destroy your PCB if left unattended for too long, are bad for the environment, and so on.

At the very least it doesn't make sense nowadays to use batteries to preserve data. Instead, use EEPROM, FRAM, flash memory, whatever, and think a bit about making it possible to reset the contents should the need arise.

No user servicable parts inside is a good maxim.

Lecture ends.

[richardc64]

Thanks for the replies.

PaulF wrote:

As far as the dedicated battery-backup ICs go, they are much easier to use than trying to implement your own design.

That's just it. My own "design" was pretty much no design at all. Never gave me any trouble, never lost data until batteries drained.

(Never had a problem mixing HC and other families, either. Maybe that was just luck.)

Now I'll be changing what I did in the past and wondered what, if any, affect the other gates in the 74HC00 would have when 5volts "goes away" on the circuits driving them.

I'll be moving point-to-point wiring on an already existing board and won't really have space for another chip.

[Dr Jefyll]

PaulF wrote:

some ICs draw less power [with CS high] than they do with CS low and WE and OE high.

A worthwhile reminder!

Windfall wrote:

At the very least it doesn't make sense nowadays to use batteries to preserve data.

Batteries do have their drawbacks. And ISTR Garth saying modern RAM's use more power during standby than RAM's from days gone by. Meanwhile, nonvolatile alternatives such as EEPROM and flash have been getting better and better. But AFAIK batteries remain the only option for Real Time Clocks, so if the battery has gotta be there anyway then some of the drawbacks are unavoidable.

richardc64 wrote:

My own "design" was pretty much no design at all. Never gave me any trouble, never lost data until batteries drained.

If you've had good results with this then I won't argue. But you haven't shown what stops the CPU when the power supply fails. You don't want the CPU trying to carry on during those moments when Vcc is decaying to 4.5V and so on -- it'd be no surprise if it crashed, and RAM corruption resulted. And the new-fangled chips generally include power-fail detection. (There are various products on the market, of course.)

When I built my own circuit, THAT was the part I wasn't happy with -- the power-fail detection.

[GARTHWILSON]

Dr Jefyll wrote:

And ISTR Garth saying modern RAM's use more power during standby than RAM's from days gone by.

That was the newer versions of Cypress' CY7C1049 512Kx8 SRAM which is no longer battery backable at super low power.

Quote:

But you haven't shown what stops the CPU when the power supply fails. You don't want the CPU trying to carry on during those moments when Vcc is decaying to 4.5V and so on -- it'd be no surprise if it crashed, and RAM corruption resulted. And the new-fangled chips generally include power-fail detection. (There are various products on the market, of course.)

When I built my own circuit, THAT was the part I wasn't happy with -- the power-fail detection.

That's "brown-out reset" which is part of the microprocessor support of most microcontrollers. There are also microprocessor-support ICs that have this as one of their features.