Connecting a AY-3-8910 to the 6502 bus.

[PaulF]

Martin_H wrote:

Good news and bad news. The good news is that adding A0 AND CLK made the BC1 line behave as expected. So my guess was correct. The bad news is that the program below should set the port A pins low, but doesn't:

Code: Select all

0500 LDA #$0E
0502 STA $7F01
0505 STZ $7F00
0508 JMP $0500

I will double check the wiring of D0-07, but it may be that D0-07 don't yet have the correct values when BDIR and BC1 transition to high. I looked at the 6502 timing diagram and those pins don't have their value until part way through CLK2, while the address bus does have a value. So that would cause BDIR and BC1 to go high, but junk data might latch rather than what I want.

Before you start pulling your hair out checking your logic and timing, have you set the bit in register 7 (If my memory serves me correctly) that sets Port A to be an output? If you havn't, you can write to register $0E endlessly and nothing will happen with the port pins.

Been there, done that...

The AY-3-8912 latches data on the falling edge of the BDIR and BC1 pulses. The fact that the data is invalid at the start of the pulses is not a problem.

[Martin_H]

OK, thanks for the information about latching on the falling edge. That means the data lines should be valid. I did not set the register to an output, so that's probably what is going on. Thanks for that information, I will try again tonight.

[Martin_H]

So I tried the following without success.

Code: Select all

    LDA  #$07    ; load the mixer I/O control register address
    STA  $7F01   ; latch the address
    LDA  #$FF    ; output mode is active high
    STA  $7F00   ; write the value to the register
    LDA  #$0E    ; load the port 1 address
    STA  $7F01   ; latch the address
    LDA  #$00    ; clear all bits
    STA  $7F00   ; write the value
    BRK             ; halt and return to monitor.

The output pins remain high.

[PaulF]

Can you post a diagram of the logic you are using, because I can't see anything wrong with your software.

[Martin_H]

At a high level the logic I want to express is the following:

7f0x = NOT /7f0x
BDIR = 7f0x AND CLK2
BC1 = BDIR AND A0 AND CLK2

To express this I am using a 4011 NAND gate and a 74HC02 NOR gate that I had in my parts box using the replacement logic:

7f0x = /7f0x NOR /7f0x
/BDIR = 7f0x NAND CLK2
BDIR = /BDIR NAND /BDIR

/A0&BDIR = A0 NAND BDIR
A0&BDIR = /A0&BDIR NOR /A0&BDIR
/BC1 = A0&BDIR NAND CLK2
BC1 = /BC1 NOR /BC1

It is a bit more convoluted, but testing with the logic probe show it seems to work. It looks like the following:

[BigDumbDinosaur]

Martin_H wrote:

At a high level the logic I want to express is the following......I am using a 4011 NAND gate and a 74HC02 NOR gate that I had in my parts box using the replacement logic

The 4011 is quite slow. You might want to work out your timing analysis and see if that may be an issue.

[Martin_H]

According to the datasheet, a 4011 can switch in about 100 ns, and I have four gates in sequence, so I would think it has a delay of about 400 ns or 0.4x10^-6 seconds. I am operating at 1 Mhz, so my period should be about 1x10^-6, ao I thought the 4011 would switch just fast enough

I have more 74hd02's, so I could rework the logic to only use NOR gates. They're supposed to switch in about 7ns or so.

[PaulF]

The 4011 is far too slow. The BDIR and BC1 pulses need to end just a few tens of nanoseconds after CLK2 goes low, before the data on the data bus becomes invalid. After the delays introduced by the 4011, the data on the data bus will be invalid long before the BDIR and BC1 pulses end and the AY-3-8910 will latch this invalid data.

Also, the cascaded logic gates are making things worse. Cascaded logic results in long propagation delays and can result in a non-functioning circuit even though the logic appears to be correct.These delays are also why you were getting invalid pulses on BC1 - the A0 line was going high before the delays in the logic let BDIR go low and the result was an invalid pulse on BC1.

At 1MHz, you need to be using 74HC logic at the least. (Or 74LS if you have a bunch of old chips floating about!) 4000 series is far too slow for 6502 work.

Here is the logic I've used for interfacing an AY-3-8910 to a 6502. I use half of a 74HC139 decoder to decode the address and CLK2, then use two gates from a 74HC00 to generate the BDIR and BC1 pulses from the decoded outputs of the 74HC139. You only get two propagation delays like this.

[Martin_H]

Thanks for the feedback and the schematic. I knew this would be a learning experience going in, and it certainly has been.

[BigDumbDinosaur]

Martin_H wrote:

Thanks for the feedback and the schematic. I knew this would be a learning experience going in, and it certainly has been.

I generally suggest that if working at 5 volts, 74HC logic is good up to around 8 MHz if there aren't more than three gates worth of propagation delay involved. Beyond that, 74AC logic or a PLD should be used. 74AC logic is generally three to five times faster than the same device in 74HC logic. Also take note that CMOS logic of any type slows down at reduced voltages.

It's a good idea to avoid mixing 74LS logic with CMOS hardware. Most CMOS devices recognize a minimum of Vcc × 0.8 volts as a valid high level, which output level cannot be attained by most 74LS devices. If you find yourself having to use a 74LS device to drive CMOS logic use the 74ACT and 74HCT families, which have TTL-compatible inputs. Be sure to carefully read data sheets to find out if other CMOS devices such as UARTs can recognize TTL levels as valid. Otherwise, you will likely end up with a DOA circuit or one that is unreliable.

[Martin_H]

I read the data sheet for the 74hc139 and they have a logic diagram for the decoder portion. It is five gates deep!

[Dr Jefyll]

Martin_H wrote:

I read the data sheet for the 74hc139 and they have a logic diagram for the decoder portion. It is five gates deep!

True enough, but the diagram isn't intended for use in estimating delays (and often such diagrams include a specific footnote to that effect).

What's important is the propagation delay for the entire section, and if you check the specifications you'll find that the "five gates deep" section has much less than five times the delay of a single gate.

I'm not qualified to explain in detail all the reasons for this, but the first gate (which inputs the outside-world signal) and the last gate (which outputs from internal logic back to the outside world) are subject to constraints which limit their speed. In contrast, the intervening gates (which deal only with on-chip signals) can be designed to be much less robust -- and a great deal faster!

[BigDumbDinosaur]

Martin_H wrote:

I read the data sheet for the 74hc139 and they have a logic diagram for the decoder portion. It is five gates deep!

When I said "three gates deep" I was referring to discrete parts. As Jeff said, the diagrams in the data sheets are intended to give you some insight into what the device is doing, not information on timing. The prop times through the device are stated in the AC performance characteristics and are how you should do your timing analysis.

[PaulF]

As Dr Jefyll and BDD have already said, although the internal logic diagram shows a chain of five gates, this doesn't mean the 74HC139 has the propagation delay of five gates. The typical propagation delay of a 74HC139 at 5V is 11ns, that of a 74HC00 at 5V is 7ns. This gives a total propagation delay through the circuit given above of 18ns. This is plenty fast enough for an AY-3-8910.

[Martin_H]

My 79HC139 arrived from Digikey and I have wired it up. But before I apply power I want to check one thing. I am only using half of it, so I assume the second decoder should be disabled by tying its enable line to 5 volts?

But should I use a pull up resistor to avoid too much current into the input, or is it current limited?