Most designs I've seen have a multiplexer on the carry input to the ALU allowing selection between

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To me it seems reasonable to add something along the lines of "L[31]" to that, or the most significant bit on the "left input bus". Its a useful bit to have access to anyway.

The "Universal device programmer" is, these days, as JTAG adaptor. You can pickup numerous FT?232 based USB dongles these days which can give you bitrates between ~12Mbit/s (older chips) to (I think) 100Mbit/s (newer ones). The FT2232 ones will probably also incorporate a (good!) USB to serial ...

Off-topic : ... (I realise this thread is old(ish), but I have been away for a while and am catching up)
Where have you been? and welcome back.

Distracted. I generally must have just forgotten about this place. With the amount of other things I juggle (of varying priorities), some things just ...

Would that be 64-bit memory, transferring a 64-bit set with each clock edge? And if so, isn't that for bursts, where the first set (long word?) takes many clocks to retrieve, and then the rest (perhaps 7 more sets) can go at one transaction per clock edge? The fact that SRAM doesn't have the burst ...

Something Mr. e2020 should think about is just what is getting accomplished at 3000 MHz. While the MPU core may be running that fast, the buses and memory subsystem are not. A contributing factor to the 65xx family's efficiency is the fact that the address and data buses are synchronous to the MPU ...

The PIC 877 (and successor 877A) have a builtin "parallel slave port" feature. While this is nowhere near as well featured as on more modern (PIC18, PIC24, dsPIC and PIC32), it should be feasible to implement a reasonably simple "command response" interface. For example, you might say that doing a ...

Why not pick an already standard SOC bus, like Wishbone or AMBA AHB? Then, not only can you easily switch cores, you can also easily drop in other components from other developers

Though note the caveats of doing so - for example, on server versions the audio stack is set into "minimum resource use mode" (rather than "sounds good mode")

For supporting more than one interrupt line, there are two options. First is you have a single IRQ vector, and the interrupt source is read from some port address or a special register. But in case a higher priority interrupt interrupts a lower priority interrupt routine, the value of this port ...

Completley forget about doing any internal logic with signals with multiple drivers.

FPGAs do not work like that. In fact, modern CMOS does not work like that. If you ask for a multi-driver bus, then the software will synthesize it poorly by building a big multiplexer somewhere for all your outputs ...

Sounds like you're maybe aiming for a day when you do actually have a DMA controller? Else, a regular ole' EIDE HDD would be ok with the multiple PIO modes right?
EIDE is a bit of a pain to implement. SCSI is standardized around a device-agnostic command and bus system. EIDE disks don't support ...

FPGAs really don't like bidirectional signals. For something designed as an FPGA soft core, you really should use separate D_in and D_out busses, and adopt a synchronous memory bus (synchronous busses scale to much higher speeds)

One advantage would be reduced code size (Obviously, 1 byte vs 3) for each call; though since BRK doesn't encode any operands and the minimum load operation would be two bytes... this is a pretty unconvincing case.

If it had been a two byte opcode, and additionally (say) loaded the operand byte ...

How can assemblers do this in two passes?

I don't know of assemblers that do that (but looking at the other comments it seems some do), but TeX (the typesetting program) does it like that:

It layouts a dokument, calculates the page numbers etc, inserts them, layouts again, recalculates, layouts ...

In the 65816 system I have on the breadboard at the moment, I have the high 8 address lines driven from both the normal 8-bit latch and also from an 8-bit buffer with all its inputs connected high. The enable lines for each chip are driven from the opposite outputs of a flip-flop so only 1 is ever ...