( The photo shows R/W, and the center portion of that waveform is identical to what will be seen on internal VSS during the same time. The center portion shows the write cycle, and during write cycles R/W is connected to internal VSS. )


I can confirm, the same waveform appeared on the poorly ...

GOT IT!

Cold solder joint on the CPU Vss pin. Gremlins were visible probing the chip pin directly, but not the rail immediately adjecent. It was additionally pre-confirmed when poking it with the scope probe ended up mechanically banishing the gremlins during the debugging session. Percussive ...

Cool, I'll get on to those measurements.

The scope is 20Mhz, dual channel. Saying a dual channel is more than 2x better. Do you mean in general utility, or could I put the second channel to good use in this context? It also has an external trigger

Thanks,

Mike

I got it under the scope. The signals look quite a lot cleaner than I was expecting. The clock looks great to me, and the ripples visible give me confidence in the fidelity of the scope, which, like I say, is pretty beaten.

The failure of R/W is clearly visible as it is pulled back towards 5V part ...

It's extremely weird for R/W to change state midway through the cycle. It's as if the CPU had been reset. Maybe /RES goes low and/or the VCC supply experiences a brownout at this point -- as it may do when bus contention arises, or when the output of a logic gate (a decoder, perhaps?) tries to ...

My apologies, I meant logic *analyser*. System clock is 2MHz, analyzer is sampling at 16, and has 16 channels showing me most of the control lines and all of the data bus at once.

To big ed: that's exactly what I am doing with my select lines, but R/W is wired directly to the relevant pins on the ...

Hi everyone!

So, it's been a while since I looked at my 6502 project. I got distracted by cycling, but recently I dug everything out, simplified my requirements and tried to produce something simple but complete.

I have a 6502, an SRAM, an EEPROM and R65C52 dual ACIA, hooked up to an FTDI ...

Assuming you'll be assembling by hand, you can also put vias in the pads themselves, further saving board space and facilitating routing and reducing inductance.

Ah, that's good to hear. I had placed a lot of vias inside pads for the reasons you mentioned, but a quick Google convinced me to ...

Thanks. I notice you're using some pretty fat power traces in various places. I don't think they're going to be delivering loads of current, does a fatter trace help reduce noise on the power lines? I imagine the opposite would be true for a signal line, although that's an intuition, and my ...

Thanks, I'll do that. By placing the caps on the underside of the board, I should be able to put them really close to the ground supply pins. I am going for a proper 4 layer board with true Vcc and ground planes on the internal layers. It's twice as expensive, but everything I've read here suggests ...

Well, several late evenings and one bored-of-hearing-about-it girlfriend later...

Here is the schematic for "release candidate 1", and an SVG of what I might sent to the board house. Unfortunately SVG is the best output I can find from Kicad's PCD editor. edit: Scratch that, the forum doesn't ...

CS_ROM is not gated by PHI2 like the other two are, I would suggest it probably should be. Also as it stands, it will be possible to write to the ROM chip - whilst this is fine, generally speaking the 28C' chips have specific requirements as to write cycles, its not like writing to RAM, so be ...

I was having some difficulty with my PDF generator, but sorted now.

Here's a correctly oriented copy, where I've also found better symbols for the RAM and ROM ICs (with logical, rather than physical schematic presentation)

So, I've been working hard when I can find the time, and I've come to the attached schematic (now presented in glorious black and white!)

It is considerably more involved that before - after looking more carefully at the serial handshaking, I decided to being the UART-USB interfaces on board.

Both ...

What I'm getting from this, more or less, is that best case is use a cpld/fpga (where a bunch of counters are "cheap", and in the fpga case at least, clock multiplication is a common feature) or hope you can work from existing signal edges. I had a Google round commercial delay ICs, they look pretty ...