No not yet.

All components has been sourced.
First draft of the CPLD code has been done and somewhat tested.
PCB design is done.

Then the summer hit!

I will pick up where I left when the wheater turns cold ... which is starting to happen now...

/norby

Just some info about the IDE CF-Card interface. In my case the OS boots and I can write and read files. So the basics work, now I have to clean-up the code and finish the docs :roll:, the first sheet with the CPU is done thanks to your library.

Great looking forward to you schematic, I would ...

Regarding Eagle, I see that you have a BUS throughout your schematic, I suppose you have not really defined the BUS with the names of all signals? Is that correct? So you just draw a connection to it without having it really connected to it.


Using busses in Eagle is very usefull and easy once ...

The '74 will produce a perfect PHI2 and PHI1 signal in sync.
Not sure how "perfect" it is but on my 275 MHz 'scope viewing the Q and /Q flop outputs on POC V1.1, the two signals appear to be dead even. So I guess from the perspective of the 65C816 and its friends, the Ø1 and Ø2 signals are perfect ...

Incidentally, I see some connections on the '245 and your '573 bank latch that don't seem to go anywhere.
Which ones? The /GOE and ALE signals? They are connected to the CPLD...
The G (output enable) input on the '245 should be driven by your /PHI2 (Ø1) clock signal, not by the CPLD. It's okay ...

Hi norby
Thanks for the library. I will soon start to draw the schematic and will let you know how it works.

As for the CF Card Interface it works. In fact I got it working approx. one hour before my first post to this thread. I use the following schematic
cf-card-decode.pdf
The /DISK signal is ...

I see two Ø2 connections attached to the CPLD. The one at the GCLK1 input (pin 83) makes sense, as your flops and state machines would be clocked from that input. What's the purpose of the Ø2 connection at the IO3 input (pin 20)?

I'm/was uncertain if the signal going into GCLK1 can also be ...

Hi Nobrby,

nice design. I see that you use a CF Card as mass storage. As I'm currently fighting with interfacing the W65C816 to the CF Card, I wanted to let you know my findings. First if you are using True IDE mode (PIN9 to ground) then you can not hot-swap the compact flash, because a newly ...

I see two Ø2 connections attached to the CPLD. The one at the GCLK1 input (pin 83) makes sense, as your flops and state machines would be clocked from that input. What's the purpose of the Ø2 connection at the IO3 input (pin 20)?

I'm/was uncertain if the signal going into GCLK1 can also be ...

After reading the DS1511 datasheet I get the impression that VBAUX can actually handle +5V.
Page 2 "Recommended DC operating conditions"
Auxiliary Battery Voltage (note 3) VBaux
Says 5.3 V max.

Later in the text they talk about 2.5V - 3.7V for VBAUX but I guess that applies to the 3.3V (W) version ...

Is the ENC28J60 any good?
The only problem I've had with the ENC28J60 module is sometimes it does not start up. I have to re-initialize it or even power cycle it for it to start. Once running, it runs very well. That issue may be caused by me and not the module, I just haven't had it happen ...

Were those really weak? BDD was talking about some kind that was really thin. These however are the same thickness as the pins that the ribbon cable on IDE hard-disc drives plug into on a PC motherboard, much thicker than IC pins. The only thing you have to be careful of is that when you pull a ...

The +/- 12 volt outputs are mandatory in the ATX2.0 and ATX-EPS standards, so they will be around for a long time. Also, power supplies have to be backward compatible with older hardware to assure interchangeability.

You are right I was confusing it with the -5V that is no longer mandatory ...

What don't you like about the memory module's connector? It can be straight pins too, so the module goes parallel to the board it's plugged into, instead of at a right angle. You could conceivably also solder the pins right into the motherboard, with no socket. No signal line is more than .2" from ...

Using the CPLD to generate a Ø2-qualified read- and write-enable signals is good and is what I'm going to be doing in POC V2. However, the RWB input on all 65xx peripheral devices has to be be valid before the rise of Ø2. Ergo the proper method is to connect all the RWB inputs on 65xx silicon to ...