BigDumbDinosaur wrote:
billylegota wrote:
Ahhh, the logic I had only checked to see if A15 was low (/CS and /OE was (A15' & PHI2)') so I need to connect A14 to /OE.
In the case of 65xx peripherals (65C22, etc.), Ø2 from your clock generator should be directly connected to Ø2 on each 65xx peripheral, RWB on the MPU must be connected directly to RWB on the 65xx peripherals, and chip selection must occur during Ø2 low and be maintained until the next fall of the clock. A failure to meet those conditions will result in a failure to operate when access to a 65xx peripheral is attempted.
WDC recommends that all timing be relative to the Ø2 clock, and that the Ø1 out and Ø2 out signals (pins 3 and 39, respectively) not be used. Here is their advisory on the matter (page 10 in the data sheet):
- An external oscillator is recommended for driving PHI2 and used for the main system clock. All production test timing is based on PHI2. PHI2O and PHI1O were used in older systems for system timing and internal oscillators when an external crystal was used.
GARTHWILSON wrote:
You must have a way to make sure RAM cannot be written when Φ2 is low! This is one way to do that. Looking at the 6502's timing diagrams in the data sheet, you will see that the address lines are not guaranteed to be valid and stable before the R/W goes low;
3. /RW comes directly from the W65C02 and goes to the VIA, ACIA, RAM, and ROM.
