Future note: gating chip selects (e.g., /CS on the ROM) with Ø2 is not a good idea if performance matters. The address bus becomes valid during Ø2 low on all 65xx MPUs, at which time chip selection should occur. The idea is to have the device ready for access as soon as Ø2 goes high. Commensurate with that is that /RD and /WD should be gated by Ø2 so those signals don't go true (low) until Ø2 is high. If using a 65C816, it is essential that no device be allowed to write to the data bus during Ø2 low, as that is when the '816 drives the data bus with the bank bits (A16-A23).

In the case of 65xx peripherals (65C22, etc.), Ø2 from your clock generator should be directly connected to Ø2 on each 65xx peripheral, RWB on the MPU must be connected directly to RWB on the 65xx peripherals, and chip selection must occur during Ø2 low and be maintained until the next fall of the clock. A failure to meet those conditions will result in a failure to operate when access to a 65xx peripheral is attempted.

WDC recommends that all timing be relative to the Ø2 clock, and that the Ø1 out and Ø2 out signals (pins 3 and 39, respectively) not be used. Here is their advisory on the matter (page 10 in the data sheet):

An external oscillator is recommended for driving PHI2 and used for the main system clock. All production test timing is based on PHI2. PHI2O and PHI1O were used in older systems for system timing and internal oscillators when an external crystal was used.

Ø1 out and Ø2 out exist primarily to allow a 65C02 to be fitted to a system that was designed with an NMOS 6502. Both signals slightly lag Ø2 by an unspecified amount, which in a high speed system, may result in difficult-to-resolve timing issues. WDC neither tests or guarantees the timing of those signals.

You must have a way to make sure RAM cannot be written when Φ2 is low! This is one way to do that. Looking at the 6502's timing diagrams in the data sheet, you will see that the address lines are not guaranteed to be valid and stable before the R/W goes low;

Have you run the DRC yet? Whether you use it or not (I don't), do a good visual on every layer. At first glance: Traces look too close to U5 pads 15-24 on the bottom layer. Even if you use an autorouter (which I don't recommend), do a good manual clean-up when it's done.

It will make it a lot easier for someone else to check it if you have one diagram with all the layers, each one shown in a different color.

That being said, there is nothing that GrafX-2 can't fix

the autorouter looks like it had a few too many drinks...

A sudden slip of the soldering iron could gouge the solder mask on one of those traces and possibly cause a bridge.

Fortunately soldermask these days seems to be awfully tough, at least if it's over bare copper rather than tinned copper. I've never had a problem with it.

The exposed trace had reflow on it, which meant that the reflow was applied before the solder mask.