Starting with my first SBC Project, Plans and Confusions

[Proxy]

BigDumbDinosaur wrote:

That philosophy is what brought about the high level of integration seen in today's computers.

on one hand it makes everything cheaper and smaller, on the other it also makes it harder to repair/see what is going on in your system.
it would be funny to have an octa-core CPU made up out of 8 seperate CPUs, maybe a future project. but i never looked into stuff like cache memory, multicore busses, etc.

BigDumbDinosaur wrote:

I tried to read your JTAG connection schematic but, once again, color is preventing me from clearly seeing what's in it.

how? the full schematic above your post is in Monochrome.

BigDumbDinosaur wrote:

OE is exactly what the name implies. That said, those pins are not dedicated to that function and can be used as regular I/O pins.

PD is "power down" and would be used to reduce power consumption when the circuit is idling. As with OE, PD can be used for regular I/O.

Other than avoiding the use of the designated JTAG pins as I/O (there is a booby-trap waiting for you if you do declare one of those pins for anything other than JTAG), and applying your clock signal (if used) to GCLK and reset to GCLR, you are free to use pins as required. However, I recommend you design your logic before you lay out the rest of the circuit and let the fitter decide how to best use the CPLD's resources.

yea turns out the datasheet shows most if not all of these, sadly not in a list that explains them directly, but via a block diagram.

also to design the logic i need to set input and output pins so i need to define where the inputs/outputs go before i make the circuit...
or am i missing something?
since you use the Chip's pin number to assign Inputs and Outputs...

[GARTHWILSON]

Proxy wrote:

it would be funny to have an octa-core CPU made up out of 8 seperate CPUs, maybe a future project. but i never looked into stuff like cache memory, multicore busses, etc.

See Andre Fachat's post at viewtopic.php?p=6194#p6194 and the topic it's in. I can't believe it's already 13 years old (and the topic was started 16 years ago!); but it's still relevant, and there are reasons we keep the archives, and further contributions to the topic would be welcome.

[BigDumbDinosaur]

Proxy wrote:

BigDumbDinosaur wrote:

I tried to read your JTAG connection schematic but, once again, color is preventing me from clearly seeing what's in it.

how? the full schematic above your post is in Monochrome.

I saw the small graphic that you said is the JTAG header and thought it was supposed to be different than the main schematic.

Quote:

also to design the logic i need to set input and output pins so i need to define where the inputs/outputs go before i make the circuit...or am i missing something?
since you use the Chip's pin number to assign Inputs and Outputs...

During the early stages of the design flow, it's best to not assign pins. For example, when I was designing the logic for my POC V2.0 unit (ATF1504AS), I declared all the inputs and outputs, but did not assign them to specific pin numbers at that time—with two exceptions:

Code: Select all

Name        glue;
PartNo      B402170001;
Date        2014/11/25;
Revision    0.5.1;
Designer    BDD;
Company     BCS Technology Limited;
Assembly    POC V2;
Location    U2;
Device      f1504ispplcc44;

property	atmel {cascade_logic=on};
property	atmel {logic_doubling=off};
property	atmel {output_fast=off};
property	atmel {pin_keep=off};
property	atmel {preassign=keep};
property	atmel {security=off};
property	atmel {xor_synthesis=on};

/*
===============
PIN ASSIGNMENTS
===============
*/
pin     1 = RESB;                                 /* system reset          */
pin       = VPA;                                  /* valid program address */
pin       = !WD;                                  /* write data            */
pin       = !RD;                                  /* read data             */
pin       = D1;                                   /* data line             */
pin       = D2;                                   /* data line             */
pin       = D0;                                   /* data line             */
pin       = !IO1;                                 /* I/O device 'B' select */
pin       = !IO0;                                 /* I/O device 'A' select */
pin       = STP;                                  /* wait-state control    */
pin       = !IO2;                                 /* I/O device 'C' select */
pin       = !IO3;                                 /* I/O device 'D' select */
pin       = !IO4;                                 /* I/O device 'E' select */
pin       = A18;                                  /* address line          */
pin       = A16;                                  /* address line          */
pin       = A17;                                  /* address line          */
pin       = RWB;                                  /* read/write            */
pin       = A15;                                  /* address line          */
pin       = A14;                                  /* address line          */
pin       = !RAM1;                                /* RAM chip select       */
pin       = !RAM0;                                /* RAM chip select       */
pin       = !ROM;                                 /* ROM chip select       */
pin       = !RST;                                 /* inverted reset        */
pin       = D3;                                   /* data line             */
pin       = A12;                                  /* address line          */
pin       = A8;                                   /* address line          */
pin       = A9;                                   /* address line          */
pin       = A10;                                  /* address line          */
pin       = A11;                                  /* address line          */
pin       = A13;                                  /* address line          */
pin    43 = PHI2;                                 /* system clock          */
pin       = VDA;                                  /* valid data address    */

What happens when you take this route is the fitter that runs following a successful compilation figures out which macrocells to use for different parts of the logic and after the fitter has done that it then assigns pins. Note that I declared only two pins: reset (pin 1) and Ø2 (PHI2) on 43. Everything else was assigned by the fitter.

If you assign pins before you've finished your logic design you may discover the source will compile but the fitter won't be able to fit the design to the CPLD. You can determine if your design will fit by examining the file xxxx.fit, where xxxx is the name of the source file. Scroll all the way to the end and you should see something such as the following:

Code: Select all

----------------  End fitter, Design FITS
$Device PLCC44 fits; JTAG ON; Secure OFF
FIT1504 completed in 0.00 seconds

That's the fitter informing you your design will fit within the constraints of your device and that the JTAG port is not to be used for logic. Here's where you need to watch out for a potential bobby-trap.

If you program a device to use the JTAG pins as logic I/O you will not be able to erase and re-program the device later on because the JTAG port will no longer be a JTAG port. Hence you must be careful to select the correct device code (f1504ispplcc44 in the above example, the isp after 1504 stands for in situ programming). Otherwise, the fitter will assume the JTAG port is not being used as a JTAG port and will likely assign those pins to something else. If the above blurb says JTAG OFF find out why before you program a device and turn it into a paperweight.

Assuming your design fits, higher up in the xxxx.fit file you will see something like the following:

Code: Select all

Performing input pin pre-assignments ...
------------------------------------
VPA assigned to pin  2
PHI2 assigned to pin  43
RESB assigned to pin  1
VDA assigned to pin  44
STP.OE equation needs patching.
1 control equation needs patching

Attempt to place floating signals ...
------------------------------------
IO0 is placed at pin 12 (MC 1)
romsel is placed at feedback node 602 (MC 2)
IO1 is placed at pin 11 (MC 3)
D0 is placed at pin 9 (MC 4)
D2 is placed at pin 8 (MC 5)
hmumcfg2 is placed at feedback node 606 (MC 6)
hmumcfg1 is placed at feedback node 607 (MC 7)
TDI is placed at pin 7 (MC 8)
hmumcfg0 is placed at feedback node 608 (MC 8)
blatch2 is placed at feedback node 609 (MC 9)
blatch1 is placed at feedback node 610 (MC 10)
D1 is placed at pin 6 (MC 11)
hiramwp is placed at foldback expander node 311 (MC 11)
ramsel is placed at feedback node 613 (MC 13)
RD is placed at pin 5 (MC 14)
extram is placed at foldback expander node 314 (MC 14)
blatch0 is placed at feedback node 615 (MC 15)
wsext is placed at foldback expander node 315 (MC 15)
WD is placed at pin 4 (MC 16)
vab is placed at foldback expander node 316 (MC 16)
A17 is placed at pin 21 (MC 17)
A16 is placed at pin 20 (MC 19)
A18 is placed at pin 19 (MC 20)
IO4 is placed at pin 18 (MC 21)
IO3 is placed at pin 17 (MC 24)
IO2 is placed at pin 16 (MC 25)
wsff is placed at feedback node 627 (MC 27)
basram is placed at feedback node 628 (MC 28)
STP.OE is placed at feedback node 629 (MC 29)
STP is placed at pin 14 (MC 30)
blatch3 is placed at feedback node 631 (MC 31)
TMS is placed at pin 13 (MC 32)
hmumcfg3 is placed at feedback node 632 (MC 32)
FB_2_vab is placed at foldback expander node 332 (MC 32)
RWB is placed at pin 24 (MC 33)
A15 is placed at pin 25 (MC 35)
A14 is placed at pin 26 (MC 36)
RAM1 is placed at pin 27 (MC 37)
RAM0 is placed at pin 28 (MC 40)
ROM is placed at pin 29 (MC 41)
RST is placed at pin 31 (MC 46)
TCK is placed at pin 32 (MC 48)
FB_3_vab is placed at foldback expander node 348 (MC 48)
D3 is placed at pin 33 (MC 49)
A12 is placed at pin 34 (MC 51)
A8 is placed at pin 36 (MC 52)
A9 is placed at pin 37 (MC 53)
TDO is placed at pin 38 (MC 56)
A10 is placed at pin 39 (MC 57)
A11 is placed at pin 40 (MC 62)
A13 is placed at pin 41 (MC 64)

                                    R     P           
                              V  V  E  V  H  G  A  A  
                     D  R  W  C  P  S  D  I  N  1  1  
                     1  D  D  C  A  B  A  2  D  3  1  
                 +------------------------------------+
                 |   6  5  4  3  2  1 44 43 42 41 40  |
              TDI| 7                               39 |A10
               D2| 8                               38 |TDO
               D0| 9                               37 |A9
              GND| 10                              36 |A8
              IO1| 11            ATF1504           35 |VCC
              IO0| 12         44-Lead PLCC         34 |A12
              TMS| 13                              33 |D3
              STP| 14                              32 |TCK
              VCC| 15                              31 |RST
              IO2| 16                              30 |GND
              IO3| 17                              29 |ROM
                 |  18 19 20 21 22 23 24 25 26 27 28  |
                 +------------------------------------+
                     I  A  A  A  G  V  R  A  A  R  R  
                     O  1  1  1  N  C  W  1  1  A  A  
                     4  8  6  7  D  C  B  5  4  M  M  
                                                1  0

The above is the pin assignments the fitter worked out for your device and design. Using that list, you would then lay out the circuit to go with the logic. That is when you assign pins.

During the fitting phase, several things are happening, one of which is the distribution of macrocells to different logic functions. Each macrocell has a limit on how many terms can be accommodated and the fitter tries to equalize macrocell usage as efficiently as possible. If you force pin assignments you may end up with a macrocell that is expected to handle more than it can, and the design won't fit.

I hope this is making some sense.

[BigDumbDinosaur]

Proxy wrote:

I'm also not 100% sure on the pinout of the JTAG connector.

See below.

JTAG Port

jtag_detail.gif (11.24 KiB) Viewed 2877 times

In my POC units, Fcc is connected to 5 volts (Vcc) through a self-resetting fuse. Be sure to liberally bypass FCC to ground with both an electrolytic (100 µF is good) and an MLCC (.1 µF is good).

[cjs]

BigDumbDinosaur wrote:

During the early stages of the design flow, it's best to not assign pins. For example, when I was designing the logic for my POC V2.0 unit (ATF1504AS), I declared all the inputs and outputs, but did not assign them to specific pin numbers at that time—with two exceptions:

Code: Select all

pin     1 = RESB;                                 /* system reset          */
...
pin    43 = PHI2;                                 /* system clock          */

So why did you assign reset and Φ2?

[Martin A]

cjs wrote:

BigDumbDinosaur wrote:

During the early stages of the design flow, it's best to not assign pins. For example, when I was designing the logic for my POC V2.0 unit (ATF1504AS), I declared all the inputs and outputs, but did not assign them to specific pin numbers at that time—with two exceptions:

Code: Select all

pin     1 = RESB;                                 /* system reset          */
...
pin    43 = PHI2;                                 /* system clock          */

So why did you assign reset and Φ2?

That would be down to the features of the ATF150x family. There are 4 "global" input only pins.

On the 1504 pin 1 is global clear, pin 2 global clock 2/output enable 2, pin 43 global clock 1, pin 44 output enable 1

[BigDumbDinosaur]

Martin A wrote:

cjs wrote:

BigDumbDinosaur wrote:

During the early stages of the design flow, it's best to not assign pins. For example, when I was designing the logic for my POC V2.0 unit (ATF1504AS), I declared all the inputs and outputs, but did not assign them to specific pin numbers at that time—with two exceptions:

Code: Select all

pin     1 = RESB;                                 /* system reset          */
...
pin    43 = PHI2;                                 /* system clock          */

So why did you assign reset and Φ2?

That would be down to the features of the ATF150x family. There are 4 "global" input only pins.

On the 1504 pin 1 is global clear, pin 2 global clock 2/output enable 2, pin 43 global clock 1, pin 44 output enable 1

Yep! Hence the fixed assignments. Furthermore, pins 2 and 44 can be used as general purpose inputs if they are not needed for their specific purposes. The fitter will use them as inputs if needed.

[Proxy]

ok, following BigDumbDinosaur's example i wrote my logic circuit without assinging pins (except Reset and the System Clock)

here is the code:

Code: Select all

Name     	65C02_SBC_v2;
PartNo   	00;
Date     	31.03.2020;
Revision 	01;
Designer 	None;
Company  	None;
Assembly 	None;
Location 	None;
Device   	f1504ispplcc44;


/* *************** INPUT PINS **********************/

PIN		1	= SYS_RST;
PIN		43	= SYS_CLK;
PIN			= RW;				/* Read(1) Write(0) */
PIN			= A0;
PIN			= A1;
PIN			= A2;
PIN			= A3;
PIN			= A4;
PIN			= A5;
PIN			= A6;
PIN			= A7;
PIN			= A8;
PIN			= A9;
PIN			= A10;
PIN			= A11;
PIN			= A12;
PIN			= A13;
PIN			= A14;
PIN			= A15;
PIN			= DIS_ROM;
PIN			= DIS_RAM;

/* *************** OUTPUT PINS *********************/

PIN			= !RDY;
PIN			= !OE_MEM;
PIN			= !WE_MEM;
PIN			= !CS_ROM;
PIN			= !CS_RAM_0;
PIN			= !CS_RAM_1;
PIN			= !RD_FT240X;
PIN			= WR_FT240X;
PIN			= !RD_STATUS;



/* ****************** LOGIC ************************/

/* Memory R/W */

OE_MEM   = (SYS_CLK & RW);
WE_MEM   = (SYS_CLK & !RW);

/* Memory Map */

CS_ROM   = A15 & A14 & A13 & DIS_ROM;
IO_EN    = A15 & A14 & !A13 & A12 & A11 & A10 & A9 & A8;
CS_RAM_0 = !CS_ROM & !IO_EN & !A15 & DIS_RAM;
CS_RAM_1 = !CS_ROM & !IO_EN & A15 & DIS_RAM;

/* IO Devices */

RD_STATUS = !IO_EN & !(A7 & A6 & A5 & A4 & A3 & A2 & A1) & A0 & SYS_CLK & RW;
RD_FT240X = !IO_EN & !(A7 & A6 & A5 & A4 & A3 & A2 & A1) & !A0 & SYS_CLK & RW;
WR_FT240X = !IO_EN & !(A7 & A6 & A5 & A4 & A3 & A2 & A1) & !A0 & SYS_CLK & !RW;

here the fitter output: LINK

(using pastebin because it's a rather long file and i don't want to waste that much space on the site)
kinda cool how it only uses up 8 out of 64 macrocells.

though i'm not sure what effects these have in your code:

Code: Select all

property   atmel {cascade_logic=on};
property   atmel {logic_doubling=off};
property   atmel {output_fast=off};
property   atmel {pin_keep=off};
property   atmel {preassign=keep};
property   atmel {security=off};
property   atmel {xor_synthesis=on};

like i know it changes how the fitter/device does some things, but what exactly i'm not sure.

BigDumbDinosaur wrote:

See below.

In my POC units, Fcc is connected to 5 volts (Vcc) through a self-resetting fuse. Be sure to liberally bypass FCC to ground with both an electrolytic (100 µF is good) and an MLCC (.1 µF is good).

oh, i didn't know i need a pullup for the JTAG pins.
but yea thanks, that pinout is the same i have on my board. so that's nice.

Martin A wrote:

cjs wrote:

So why did you assign reset and Φ2?

That would be down to the features of the ATF150x family. There are 4 "global" input only pins.

On the 1504 pin 1 is global clear, pin 2 global clock 2/output enable 2, pin 43 global clock 1, pin 44 output enable 1

actually there are 3 global clocks. Pin 43 (GCLK1), Pin 2 (GCLK2), and Pin 41 (GCLK3).

[BigDumbDinosaur]

Proxy wrote:

though i'm not sure what effects these have in your code:

Code: Select all

property   atmel {cascade_logic=on};
property   atmel {logic_doubling=off};
property   atmel {output_fast=off};
property   atmel {pin_keep=off};
property   atmel {preassign=keep};
property   atmel {security=off};
property   atmel {xor_synthesis=on};

Here's a quick explanation. You will need to read the Microchip literature for more details.

• property atmel {cascade_logic=on}; <—— Allows sharing of Pterms between macrocells, thus making it possible for very complex logic to be fitted. In simpler designs, you can leave this off and thus speed up the fitting process.
• property atmel {logic_doubling=off}; <—— A proprietary Atmel design feature that makes better use of available resources in highly complex designs by providing more internal logic paths than competing designs. I recommend you leave it off if most of your design is combinatorial logic. Logic doubling is best used in applications that make heavy use of state machines.
• property atmel {output_fast=off}; <—— Controls the slew rate of output pins. If on, output slew rate is dramatically increased. Observation on my scope suggests about a 3:1 speedup, approaching a one nanosecond transition time (however my scope is a 275 MHz unit, so I'm inferring this from what I am seeing). A one nanosecond rise and fall is brutal when it comes to noise and ringing. If you want to use this feature you will need to do a circuit analysis so the CPLD's outputs are impedance-matched to whatever it is they are driving. Otherwise, your unit may not work well, or at all.
• property atmel {pin_keep=off}; <—— If turned on, pins will "remember" their most recent state, even when set to high-Z. In most cases, this feature should be turned off.
• property atmel {preassign=keep}; <—— This tells the fitter to not change any pin number assignments made in the source file, e.g., the clock input assignment. Otherwise, the fitter might ignore your pin numbers and assign its own.
• property atmel {security=off}; <—— If turned on, the security fuse in the CPLD will be "blown" following a successful programming session, preventing anyone from read back the contents of the device. The only way to "unblow" the security fuse is to erase the device through the JTAG port.
• property atmel {xor_synthesis=on}; <—— Exclusive-OR gates are not usually part of a CPLD's logic fabric but can be synthesized with the use of internal nodes. For most applications, you can leave this on. If the fitter is having trouble fitting a complex design you may be able to get over it by turning off this feature.

[Proxy]

BigDumbDinosaur wrote:

Here's a quick explanation. You will need to read the Microchip literature for more details.

• property atmel {cascade_logic=on}; <—— Allows sharing of Pterms between macrocells, thus making it possible for very complex logic to be fitted. In simpler designs, you can leave this off and thus speed up the fitting process.
• property atmel {logic_doubling=off}; <—— A proprietary Atmel design feature that makes better use of available resources in highly complex designs by providing more internal logic paths than competing designs. I recommend you leave it off if most of your design is combinatorial logic. Logic doubling is best used in applications that make heavy use of state machines.
• property atmel {output_fast=off}; <—— Controls the slew rate of output pins. If on, output slew rate is dramatically increased. Observation on my scope suggests about a 3:1 speedup, approaching a one nanosecond transition time (however my scope is a 275 MHz unit, so I'm inferring this from what I am seeing). A one nanosecond rise and fall is brutal when it comes to noise and ringing. If you want to use this feature you will need to do a circuit analysis so the CPLD's outputs are impedance-matched to whatever it is they are driving. Otherwise, your unit may not work well, or at all.
• property atmel {pin_keep=off}; <—— If turned on, pins will "remember" their most recent state, even when set to high-Z. In most cases, this feature should be turned off.
• property atmel {preassign=keep}; <—— This tells the fitter to not change any pin number assignments made in the source file, e.g., the clock input assignment. Otherwise, the fitter might ignore your pin numbers and assign its own.
• property atmel {security=off}; <—— If turned on, the security fuse in the CPLD will be "blown" following a successful programming session, preventing anyone from read back the contents of the device. The only way to "unblow" the security fuse is to erase the device through the JTAG port.
• property atmel {xor_synthesis=on}; <—— Exclusive-OR gates are not usually part of a CPLD's logic fabric but can be synthesized with the use of internal nodes. For most applications, you can leave this on. If the fitter is having trouble fitting a complex design you may be able to get over it by turning off this feature.

alright, it had pin_keep on so i had to turn that off. and for safety i also manually disabled security, even though it was already off.

i used the list it generated to assign the pins on my Schematic. but i noticed it doesn't list the RST or RDY pin, probably because internally neither are used, so it just ignored it.
I will still keep the RST line on pin 1, but i can remove the RDY line from the CPLD since the system seems to be running fine without a RDY circuit anyways.

but now i have exactly 1 IO pin left. should i just leave it unconnected, pull it to ground, or set it to an output in WinCUPL? (it's pin 41).
I don't know if assigning that one pin would change the rest as well...

well after running freerouting and forgetting about the pin i just thought of it again... and it's completely encased. i can't even make a connection to ground. in theory i could just connect it to the SYS_CLK which is a pin right next to it, and pin 41 is a GCLK after all so there should be nothing bad about doing that, right?

[BigDumbDinosaur]

Proxy wrote:

i used the list it generated to assign the pins on my Schematic. but i noticed it doesn't list the RST or RDY pin, probably because internally neither are used, so it just ignored it.

That's correct behavior. Not only must a pin be assigned it must be referred to in at least one logic statement. Otherwise, the fitter will make it a no-connect.

Quote:

but now i have exactly 1 IO pin left. should i just leave it unconnected, pull it to ground, or set it to an output in WinCUPL? (it's pin 41).

If the pin is not assigned in your source code it will be internally "unconnected," being neither an input or output. It should be left floating. In their app notes, Microchip advises to not connect anything to an unused pin.

Quote:

in theory i could just connect it to the SYS_CLK which is a pin right next to it, and pin 41 is a GCLK after all so there should be nothing bad about doing that, right?

In theory, any pin that is capable of accepting input can be assigned the clock input role. I believe the GCLK pins exist for use with state machines and that in some cases, a logic equation that refers to a clock may not fit if the clock is not on a GCLK pin. I suggest you stick with GCLK1 for accepting Ø2.

[Proxy]

ok i've been postponing ordering the boards and parts for a few days now...
again i've been too scared to order anything because i don't want to miss any mistakes i could've made, that could result in more board ordering...

I've been procastinating by mostly gaming but also by making this:

it should be kinda self explanatory. (i tried to avoid using too many or any colors. so it's mostly black/gray/white)

i liked how clean to look at this Opcode matrix is: https://www.masswerk.at/6502/6502_instruction_set.html
but sadly i was unable to find such a clean version for the 65C02.
sure you got the datasheet and sites like this: http://www.oxyron.de/html/opcodesc02.html but neither are that great to look at...
so i just made my own!
i know the 65C02 has some different cycle counts on some instructions, but pfffft. who needs that.

i also made these 2 tables to show off all addressing modes for Loads and Arithmetic/Logic instructions:

Cyan instructions = 65C02 exclusive
tell me if there are some wrong cycle counts or missing instructions.
no idea if these are useful to anyone.

.

anyways i should stop with this and just order the damn boards. i've checked over the PCB in KiCad multiple times and didn't find any mistakes. i checked the files generated by WinCUPL and compared it to the PCB (which is pointless as i can always change the pinout of the program if i did make a mistake there).
the only thing holding me back from ordering all the stuff is fear that i somehow still missed something... and i don't know how to work against that.

[drogon]

Proxy wrote:

ok i've been postponing ordering the boards and parts for a few days now...
again i've been too scared to order anything because i don't want to miss any mistakes i could've made, that could result in more board ordering...

Sometimes you just have to do it and start somewhere (with PCB). Then when you want to make changes... well... you do this...

then you think about ordering a new PCB

-Gordon

[Proxy]

ok i finally ordered the PCBs, ordering all the stuff from Mouser was a bit harder though.
mostly because it was >100 EUR worth of stuff.
in it was:
* The 3 state driver, which should hopefully be fast enough for the system (SN74AHC541N)
* The power switch for the PCB
* The ATF1504AS, the fitting sockets, a PLCC chip puller, and the programmer thingy from Atmel
* A DIP chip puller, since i currently don't have one and constantly removing a FLASH chip with a screwdriver is annoying and can bend pins.
* Desoldering wick, better than using a stripped copper wire soaked in flux.

that is hopefully everything i need.

[Chromatix]

Interesting instruction tables. In the one for transfers, don't forget the stack as a memory addressing mode.

I would try structuring the opcode table with a different grouping of bits, which better reflects the way opcodes are internally decoded by the 6502. Broadly speaking there is an aaabbbcc pattern, which gets confused if you make the table "square" with an xxxxyyyy pattern. I think it makes sense to have rows with the aaa000cc bits, and columns with 000bbb00 bits.