Proxy wrote:
BigDumbDinosaur wrote:
I tried to read your JTAG connection schematic but, once again, color is preventing me from clearly seeing what's in it.
how? the full schematic above your post is in Monochrome.
I saw the small graphic that you said is the JTAG header and thought it was supposed to be different than the main schematic.
Quote:
also to design the logic i need to set input and output pins so i need to define where the inputs/outputs go before i make the circuit...or am i missing something?
since you use the Chip's pin number to assign Inputs and Outputs...
During the early stages of the design flow, it's best to not assign pins. For example, when I was designing the logic for my POC V2.0 unit (ATF1504AS), I declared all the inputs and outputs, but did not assign them to specific pin numbers at that time—with two exceptions:
Code:
Name glue;
PartNo B402170001;
Date 2014/11/25;
Revision 0.5.1;
Designer BDD;
Company BCS Technology Limited;
Assembly POC V2;
Location U2;
Device f1504ispplcc44;
property atmel {cascade_logic=on};
property atmel {logic_doubling=off};
property atmel {output_fast=off};
property atmel {pin_keep=off};
property atmel {preassign=keep};
property atmel {security=off};
property atmel {xor_synthesis=on};
/*
===============
PIN ASSIGNMENTS
===============
*/
pin 1 = RESB; /* system reset */
pin = VPA; /* valid program address */
pin = !WD; /* write data */
pin = !RD; /* read data */
pin = D1; /* data line */
pin = D2; /* data line */
pin = D0; /* data line */
pin = !IO1; /* I/O device 'B' select */
pin = !IO0; /* I/O device 'A' select */
pin = STP; /* wait-state control */
pin = !IO2; /* I/O device 'C' select */
pin = !IO3; /* I/O device 'D' select */
pin = !IO4; /* I/O device 'E' select */
pin = A18; /* address line */
pin = A16; /* address line */
pin = A17; /* address line */
pin = RWB; /* read/write */
pin = A15; /* address line */
pin = A14; /* address line */
pin = !RAM1; /* RAM chip select */
pin = !RAM0; /* RAM chip select */
pin = !ROM; /* ROM chip select */
pin = !RST; /* inverted reset */
pin = D3; /* data line */
pin = A12; /* address line */
pin = A8; /* address line */
pin = A9; /* address line */
pin = A10; /* address line */
pin = A11; /* address line */
pin = A13; /* address line */
pin 43 = PHI2; /* system clock */
pin = VDA; /* valid data address */
What happens when you take this route is the fitter that runs following a successful compilation figures out which macrocells to use for different parts of the logic and after the fitter has done that it then assigns pins. Note that I declared only two pins: reset (pin 1) and Ø2 (PHI2) on 43. Everything else was assigned by the fitter.
If you assign pins before you've finished your logic design you may discover the source will compile but the fitter won't be able to fit the design to the CPLD. You can determine if your design will fit by examining the file
xxxx.fit, where
xxxx is the name of the source file. Scroll all the way to the end and you should see something such as the following:
Code:
---------------- End fitter, Design FITS
$Device PLCC44 fits; JTAG ON; Secure OFF
FIT1504 completed in 0.00 seconds
That's the fitter informing you your design will fit within the constraints of your device and that the JTAG port is not to be used for logic. Here's where you need to watch out for a potential bobby-trap.
If you program a device to use the JTAG pins as logic I/O you will not be able to erase and re-program the device later on because the JTAG port will no longer be a JTAG port. Hence you must be careful to select the correct device code (
f1504ispplcc44 in the above example, the
isp after
1504 stands for
in situ programming). Otherwise, the fitter will assume the JTAG port is not being used as a JTAG port and will likely assign those pins to something else. If the above blurb says JTAG OFF find out why before you program a device and turn it into a paperweight.
Assuming your design fits, higher up in the
xxxx.fit file you will see something like the following:
Code:
Performing input pin pre-assignments ...
------------------------------------
VPA assigned to pin 2
PHI2 assigned to pin 43
RESB assigned to pin 1
VDA assigned to pin 44
STP.OE equation needs patching.
1 control equation needs patching
Attempt to place floating signals ...
------------------------------------
IO0 is placed at pin 12 (MC 1)
romsel is placed at feedback node 602 (MC 2)
IO1 is placed at pin 11 (MC 3)
D0 is placed at pin 9 (MC 4)
D2 is placed at pin 8 (MC 5)
hmumcfg2 is placed at feedback node 606 (MC 6)
hmumcfg1 is placed at feedback node 607 (MC 7)
TDI is placed at pin 7 (MC 8)
hmumcfg0 is placed at feedback node 608 (MC 8)
blatch2 is placed at feedback node 609 (MC 9)
blatch1 is placed at feedback node 610 (MC 10)
D1 is placed at pin 6 (MC 11)
hiramwp is placed at foldback expander node 311 (MC 11)
ramsel is placed at feedback node 613 (MC 13)
RD is placed at pin 5 (MC 14)
extram is placed at foldback expander node 314 (MC 14)
blatch0 is placed at feedback node 615 (MC 15)
wsext is placed at foldback expander node 315 (MC 15)
WD is placed at pin 4 (MC 16)
vab is placed at foldback expander node 316 (MC 16)
A17 is placed at pin 21 (MC 17)
A16 is placed at pin 20 (MC 19)
A18 is placed at pin 19 (MC 20)
IO4 is placed at pin 18 (MC 21)
IO3 is placed at pin 17 (MC 24)
IO2 is placed at pin 16 (MC 25)
wsff is placed at feedback node 627 (MC 27)
basram is placed at feedback node 628 (MC 28)
STP.OE is placed at feedback node 629 (MC 29)
STP is placed at pin 14 (MC 30)
blatch3 is placed at feedback node 631 (MC 31)
TMS is placed at pin 13 (MC 32)
hmumcfg3 is placed at feedback node 632 (MC 32)
FB_2_vab is placed at foldback expander node 332 (MC 32)
RWB is placed at pin 24 (MC 33)
A15 is placed at pin 25 (MC 35)
A14 is placed at pin 26 (MC 36)
RAM1 is placed at pin 27 (MC 37)
RAM0 is placed at pin 28 (MC 40)
ROM is placed at pin 29 (MC 41)
RST is placed at pin 31 (MC 46)
TCK is placed at pin 32 (MC 48)
FB_3_vab is placed at foldback expander node 348 (MC 48)
D3 is placed at pin 33 (MC 49)
A12 is placed at pin 34 (MC 51)
A8 is placed at pin 36 (MC 52)
A9 is placed at pin 37 (MC 53)
TDO is placed at pin 38 (MC 56)
A10 is placed at pin 39 (MC 57)
A11 is placed at pin 40 (MC 62)
A13 is placed at pin 41 (MC 64)
R P
V V E V H G A A
D R W C P S D I N 1 1
1 D D C A B A 2 D 3 1
+------------------------------------+
| 6 5 4 3 2 1 44 43 42 41 40 |
TDI| 7 39 |A10
D2| 8 38 |TDO
D0| 9 37 |A9
GND| 10 36 |A8
IO1| 11 ATF1504 35 |VCC
IO0| 12 44-Lead PLCC 34 |A12
TMS| 13 33 |D3
STP| 14 32 |TCK
VCC| 15 31 |RST
IO2| 16 30 |GND
IO3| 17 29 |ROM
| 18 19 20 21 22 23 24 25 26 27 28 |
+------------------------------------+
I A A A G V R A A R R
O 1 1 1 N C W 1 1 A A
4 8 6 7 D C B 5 4 M M
1 0
The above is the pin assignments the fitter worked out for your device and design. Using that list, you would then lay out the circuit to go with the logic. That is when you assign pins.
During the fitting phase, several things are happening, one of which is the distribution of macrocells to different logic functions. Each macrocell has a limit on how many terms can be accommodated and the fitter tries to equalize macrocell usage as efficiently as possible. If you force pin assignments you may end up with a macrocell that is expected to handle more than it can, and the design won't fit.
I hope this is making some sense.
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