I noticed one anomaly (or feature?) while manually clocking a 6502 through the reset sequence using a microcontroller with a "blind interface" to the 6502. When I accidentally started the reset sequence with CLK lo instead of hi, effectively issuing 1½ clocks instead of 2 full clocks while RESET was lo, I needed 8 clocks instead of 7 clocks to load the reset vector after setting the RESET pin hi. Knowing exactly how many clocks is important for synchronizing the uC "blind interface" functions to the CPU.
/******************************************************************************
* uC 'blind interface' core routines *
* */
void uReset() // ****************************************
{ clk(1); // clock = 1 *
res(0); // reset = 0 ~~~~~~~~~~~~~~~~~~~~~~~~~~ *
uPull(ram); // (1) *
uPull(ram); // (2) *
res(1); // reset = 1 ~~~~~~~~~~~~~~~~~~~~~~~~~~ *
uPull(ram); // (1) *
uPull(ram); // (2) *
uPull(ram); // (3) *
uPull(ram); // (4) *
uPull(ram); // (5) *
uPush(lo(0x8000)); // address $FFFC (reset vector lo) (6) *
uPush(hi(0x8000)); // address $FFFD (reset vector hi) (7) *
} // ****************************************
void wrROM(u16 address,byte data) // ****************************************
{ uPush(0xA9); // lda <imm> *
uPush(data); // " *
uPush(0x8D); // sta <abs> *
uPush(lo(address)); // " address lo *
uPush(hi(address)); // " address hi *
uPull(rom); // " 6502 write op' *
} // ****************************************
void wrRAM(byte data) // ****************************************
{ uPush(0xA9); // lda <imm> *
uPush(data); // " *
uPush(0x8D); // sta <abs> *
uPush(lo(addr)); // " abs address lo *
uPush(hi(addr)); // " abs address hi *
uPull(ram); // " 6502 write op' *
} // ****************************************
byte rdMEM(byte mem) // ****************************************
{ uPush(0x4C); // jmp $8000 reset PC (avoid I/O area) *
uPush(lo(0x8000)); // " abs address lo *
uPush(hi(0x8000)); // " abs address hi *
uPush(0xAD); // lda <abs> *
uPush(lo(addr)); // " abs address lo *
uPush(hi(addr)); // " abs address hi *
return uPull(mem); // " 6502 read op' *
} // ****************************************
/******************************************************************************
* load 64K RAM from 64K 'A' or 'B' half of ROM at 'power-up' or 'reset' at *
* a nice liesurely 1-MHz rate. *
* */
void loader() // ****************************************
{ addr = 0x0000; x15(0); // start address $0000, ROM A15 = 0 *
uReset(); // reset CPU (synchronize micro to cpu) *
do // copy 64K ROM minus 8K I/O area to RAM *
{ wrRAM(rdMEM(rom)); // ROM -> RAM (0000..5FFF & 8000..FFFF) *
if(++addr == 0x6000) // if I/O area ($6000..$7FFF) *
{ addr = 0x8000; x15(1); // skip, ROM A15 = 1 ($8000..$FFFF) *
} // *
} while(addr); // until roll-over to 0 (full 64K image) *
} // ****************************************
/******************************************************************************
* 6502 "RUN" mode (disconnect uC, reset 6502, start CPU clock, select RAM) *
* */
void runMode() // **** switch over to 6502 'RUN' mode ****
{ res(0); // reset = 0 *
beginClock(); // start 1, 2, 4, or 8 MHz CPU clock *
busInp(); // disconnect Nano from data bus (hi-z) *
// pullUp(); // enable Nano data bus weak pull-ups *
// endSerial(); // disconnect Nano from usb adapter *
PORTC = ram; // enable RAM *
res(1); // reset = 1 -> 6502 'run' *
} // ****************************************
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