First off, thank you for this VERY detailed response George. I really appreciate the time you took on it.
gfoot wrote:
Have you made a prototype already or are you going straight to PCB?
I'm so anti-breadboard right now that I have not made any prototype. I will be printing it and if it doesn't work, printing again later!
gfoot wrote:
I think there may be an issue with the timing between U15 and U16. Firstly, you're using a latch at U15 - I think a flipflop would be better. The issue is that your latch is going to reload whatever is on the data bus throughout half of the eight-pixel cycle (when H4 is low), and for the early part of that time the data on the bus won't be stable (it takes a while for the transceivers U13,U14,U18,U19 to swap over, for the RAM to look up the new address, and for its data outputs to stabilise on the data bus as inputs to U15).
I had been thinking and debating this for a long while. Here's my quick reasoning, and then I'll elaborate on timing. A pro for the latch is that the pixel data from RAM is not changing during that low cycle anyways, so leaving LE high doesn't affect actual output. A con against the flip-flop is that the timing delay, that you were mentioning, could be off, resulting the wrong data being on the flip-flop, which would of course throw everything off.
But the point you are making is that the latch will have data from who knows where while the 244's are still switching over. Lets go through some timing:
First, H4 (which is PHI2) goes low. The 6502 is coming off of the address bus and counters are wanting on the address bus. The propagation delay on the 244's is 9ns and the enable delay is 13ns, so basically 13ns to get onto the address bus. Then it hits the RAM which is 55ns, then it comes back to the '373 latch at a total of 68ns. My full low clock is 158ns, so the data will definitely be latched! BUT what is the latch outputting before the 68ns? Before H4 went low, we had the previous color data. The propagation delay for LE to Q is 15ns, so I will definitely be putting something *else* on the latch for some time. Does that affect output? So H2 goes low and high every 79ns. So from H2 low to H2 high, we have only 11ns where the ACTUAL color data is on the latch, and with 15ns on the '153, well, disaster. After H2 goes high things are back to normal.
So indeed, there must be some other type of delay, as you were mentioning later, H1 could be used. Thank you for spotting this George.
gfoot wrote:
In my designs I use a flipflop here and clock it at (or slightly before) the end of the half of the cycle when the video system owns the bus, so that there's been a whole half cycle of time for that data to become stable at that point, and we're about to release the bus to the CPU.
So in a way, during your low PHI2, you are outputting Color Pixel 3, and then the new Color Pixel 0. PHI2 goes high and you are outputting Color Pixel 1 and then Color Pixel 2? I was thinking about this, and it seems like it would be an issue of consistency BUT because it's all continuous, it shouldn't matter. I might have 1 blank pixel on the left side, nothing to worry about.
gfoot wrote:
Another issue is with the timing of U16 - I tried something similar, for 320x480, using a quad 2-to-1 multiplexer to split out two pixels of data. The issue was that it's hard to ensure the multiplexer switches in sync with the point at which the new data is loaded into the latch U15 (or flipflop in my case, as I said above). In your case I believe this would be when H2 and H4 are both falling. The latch may operate faster than U16, and present new data before U16 changes which bits it is selecting; or slower, in which case U16 might change first, briefly outputting an old pixel value.
The propagation delay for the '153 is 15ns, which is essentially the same as the '373. If there is any differentiation, we are talking not but a couple of nanoseconds. I know VGA is picky, but I don't think I could clean up a signal into the single digit nanoseconds. When exactly is the monitor accepting the incoming signal as the pixel color? At the very beginning?
gfoot wrote:
A solution to this is to put yet another flipflop on the other side of the multiplexer, clocked just after the multiplexer (and possibly the latch/flipflop U15) change state, so that there's a little time for both U15 and U16 to do their jobs and U16 to output the correct new signal. e.g. I think you could clock this flipflop with an inverted or otherwise slightly delayed H1 to achieve that. I would then pass HSYNC and VSYNC through that same flipflop, so that all transitions of the signals going to the monitor are in time with some master clock (in this case H1 rather than the VGA clock, but that should be fine as all the HSYNC boundaries are even numbers).
Though of course this a great idea, is it required? How required? I am definitely able to get a nice solid picture without passing HSYNC and VSYNC through additional flipflops. My previous design was not bad in timing at all, the only issue was when I tried to *alter* the data. My reasoning then is that the monitor will display what it displays, and the signals don't need to be spot-on perfect. I am not a spot-on perfect kind of guy!
I definitely get what you are saying though. If they are all lined up, and you shoot them into the VGA all at the exact same time, there will never be any issues. Totally get it. I will be thinking about it George, thank you.
gfoot wrote:
I didn't check the logic gates in detail but it also looks like your RAM is not active for the range that you stated in the notes on the schematic - it's only active for 0000-7EFF, and ~IO signal goes low for 7F00-7FFF, but the VIA is also only active for half that range because one of its CS lines is fed by A7. This might be fine, I just point it out because it differs from the notes.
That was a BIG GOOF on my part! Sorry. I apparently had shifted everything over one hexa-digit. Correct, 7EFF, not 7FEF or something. Dyslexia
The schematic is good, those notes were incorrectly typed. Thank you, I corrected them now.
So! The biggest question is: should I replace the '373 with a '374 instead? And if so, do I then use H1 to trigger the flip flops? I'll also be thinking about the '153, and perhaps a flip-flop after that one (with sync signals). Hm.
Thank you for this again George. I really appreciate it. I'll keep updating on changes. It was very good to have a second set of eyes!
Chad