Timing for a multi-processor shared memory 65816 system

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BigDumbDinosaur
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Re: Timing for a multi-processor shared memory 65816 system

Post by BigDumbDinosaur »

BigEd wrote:
So, a hobbyist can hope for 20MHz operation, and that's outside the specification.

If the parts are being tested under production conditions at 20 MHz it should be possible to run at that speed at room temperature and with a solid 5 volt power source. However, as I said, it's not guaranteed. And, of course, glue logic timing and other factors can cause a design to “hit the wall” at a much lower clock rate.

Quote:
Edit: but hobbyists, especially beginners, find it difficult to debug an unreliable build. So, neglecting to put in some margin is courting disappointment.

Agreed, especially if building on a breadboard. Better to run slowly and see some positive results than run fast and see no results.
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plasmo
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Re: Timing for a multi-processor shared memory 65816 system

Post by plasmo »

BigEd wrote:
So, a hobbyist can hope for 20MHz operation, and that's outside the specification.
Regarding W65C816, hobbyists can expect 30MHz operation and hope for 40MHz. No real-world product would go past 14Mhz because that is the legal limit. This is like the speedometers are marked past 120MPH but the legal speed limit is 70MPH; the 120MPH or more is for the hobbyists. Yes, it is very dangerous to go 120MPH.
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Re: Timing for a multi-processor shared memory 65816 system

Post by BigEd »

Have we seen reliable 30MHz '816 operation? I may have forgotten!
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Re: Timing for a multi-processor shared memory 65816 system

Post by BigDumbDinosaur »

plasmo wrote:
Yes, it is very dangerous to go 120MPH.

Only if you run into something. :D

BTW, I have gone somewhat faster than 120. My (now-retired) drag car could do low 8 second, 160 MPH quarter-miles.

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Re: Timing for a multi-processor shared memory 65816 system

Post by BigDumbDinosaur »

BigEd wrote:
Have we seen reliable 30MHz '816 operation? I may have forgotten!

Someone had reported getting a minimal system running that fast. Try as I might, I can't seem to find the topic.
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Re: Timing for a multi-processor shared memory 65816 system

Post by BigEd »

I could find confident and hopeful forward-looking statements, that it should be possible, but we all know that's not quite the same as building a reliable machine!
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Re: Timing for a multi-processor shared memory 65816 system

Post by GARTHWILSON »

BigDumbDinosaur wrote:
BigEd wrote:
Have we seen reliable 30MHz '816 operation? I may have forgotten!

Someone had reported getting a minimal system running that fast. Try as I might, I can't seem to find the topic.
You might be thinking of plasmo's experiments he tells about in this post viewtopic.php?p=85784#p85784 where he writes at the end,
Quote:
Edit:
By buffering oscillator output with CPLD, I'm able to run W65C02 at 36MHz, but I noticed it will crash when voltage is lowered to 4.6V, so it is nearing the edge at 36MHz. By raising voltage above 5.3V, I can run successfully at 40MHz, but that's definitely outside of the commercial operating voltage. All tests are done at room temperature.
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Re: Timing for a multi-processor shared memory 65816 system

Post by BigEd »

Ah, good find!
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Re: Timing for a multi-processor shared memory 65816 system

Post by plasmo »

BigDumbDinosaur wrote:
Only if you run into something. :D
Speed is not the problem, it is SUDDEN stop that maims and kills :wink:
I'm not a car person, but that reminds me of a Cobra roadster.

That W65C816 overclock experiment showed W65C816 can be overclocked just as recklessly as W65C02, possibly even more. I have successful overclocked a number of W65C02 SBC to 29.49MHz, so I believe similarly designed W65C816 SBC can also reach 29.49MHz. In fact, I did an experiment modifying the W65C02 SBC to accommodate W65C816. I plan to layout a new version of pc board that can accommodate both W65C02 and W65C816.
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AndrewP
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Re: Timing for a multi-processor shared memory 65816 system

Post by AndrewP »

Speaking of speed being the problem... or at least the sudden change. I was curious what would happen if I wired a '74 D-type edge triggered flip flop into a 100Mhz clock.

The result was pretty bad.

Basically I have 100Mhz clock oscillator connected to an unbuffered inverter and from there into a D-type flip flop all on soldered strip-board.

So my question is: What have I done (or not done?) What is going on?
  • Am I missing a vital component?
  • The circuit is about 9cm by 6cm, does that make the connections too big?
  • Is it because I'm (obviously) missing a ground plane?
  • Are my oscilloscope probes junk? (They're the default Siglent 200Mhz jobbies)
  • Is a 100Mhz signal on strip-board possible in anyway?
  • Other things that I don't know that I don't know...
Clock-schematic.png
The 2200uF cap was me trying to work out how to get signal off my 3.3V line. It doesn't seem to have any significant effect on anything.
Clock-signal.png
Seriously, what is going on in here? The yellow 100MHz clock signal is very small (about 1V peak-to-peak) but the data sheet for the LVCMOS oscillator indicates it should be 10% VDD (3.3V) to 90% VDD. This could well be my oscilloscope probes, they're rated at 200MHz but I've seen reviews saying they're rubbish.

The purple 3.3V line is wobbling by about half the height of the clock signal? And so is ground which makes it really hard to tell what the 'scope is truly using for reference.

The green 50Mhz signal is at least going above 2.4V and below 0.4V but I'd expected that it would have been "square'er" as it's driven by Schmitt triggered inverted, three of them. Although their datasheet says worst case propagation time is 4ns and as the clock rise / fall time is 5ns. It's wired as a clock divider with /Q into D.

The cyan 25MHz signal is the 50MHz signal wired into the unused side of the flip flop.
Clock-built.jpg
The top row is unused (5V).
the second row is 3.3V.
the third row is 0V.

This build was for curiosity's sake but should I build it on a PCB to see the difference? Is it worth it?

Ultimately what I was trying to do was get a nice square 50Mhz clock signal.
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Dr Jefyll
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Re: Timing for a multi-processor shared memory 65816 system

Post by Dr Jefyll »

AndrewP wrote:
Are my oscilloscope probes junk? (They're the default Siglent 200Mhz jobbies)
What about the 'scope itself -- what is its bandwidth?

Whether it's the scope or the probes or both, there's pretty clearly something limiting bandwidth. Notice how the signal that appears to have the lowest amplitude is the signal that's the highest frequency? And the lowest frequency signal appears to have the highest amplitude?

And BTW let me remind you that a scope rated for, say, 100 MHz, will do an alright job of displaying a 100 MHz sine wave but it will disappoint you if you hope to view a 100 MHz square wave. The square wave will appear to be almost a sine wave. That's because a square wave is actually a mixture of frequencies including the fundamental frequency plus a series of harmonics -- fundamental times 2, times 3, times 4 etc. Obviously the harmonics are beyond the scope's ability to properly display.

Your construction technique isn't great but it's not utterly horrible either. A ground plane is desirable but not mandatory for a job like this.

-- Jeff
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Re: Timing for a multi-processor shared memory 65816 system

Post by BigEd »

(That's fundamental times 3, I think, for a square wave, which is even worse.)

One thing that might be worth trying is to feed this clock-like signal into a divider. Then you can be trying to measure a 25MHz or 5MHz clock, which you can do with much more confidence.

But bear in mind, even 30MHz is on the high side for ad-hoc construction techniques. 100MHz is very hopeful.
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Re: Timing for a multi-processor shared memory 65816 system

Post by Dr Jefyll »

BigEd wrote:
One thing that might be worth trying is to feed this clock-like signal into a divider. Then you can be trying to measure a 25MHz or 5MHz clock, which you can do with much more confidence.
Good idea. Or, alternatively, just swap out the 100 MHz oscillator for one that's much lower.
Quote:
[...] for ad-hoc construction techniques. 100MHz is very hopeful.
I believe the circuit is working. Even though the instruments don't show the waves as being square, it's possible to make out the 2:1 and 4:1 frequency ratios.

Still, it'd be less confusing if lower frequencies were chosen -- within the range that can be properly displayed.

-- Jeff
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html
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Re: Timing for a multi-processor shared memory 65816 system

Post by BigDumbDinosaur »

AndrewP wrote:
Speaking of speed being the problem... or at least the sudden change. I was curious what would happen if I wired a '74 D-type edge triggered flip flop into a 100Mhz clock...This could well be my oscilloscope probes, they're rated at 200MHz but I've seen reviews saying they're rubbish.

Are your probes “compensated?” At the frequencies you are exploring, non-compensated ones are likely distorting the daylights out of what should be a square-wave signal. A compensated probe will have an adjustment to “tune” the probe to the scope's input for most accurate signal rendition.

Square waves consist of the fundamental and a series of odd-order harmonics. A theoretically-pure square wave contains no even-order harmonics, and the harmonic progression goes out to infinity. Practical devices cannot achieve that but in the case of fast logic, can produce a harmonic progression that is at least 20× the fundamental.

Realistically, your instruments need to have at least 10× the bandwidth of the square wave's fundamental in order properly display a reasonable facsimile of a square wave. A 200 MHz scope is not going to cut it at 100 MHz, no matter how good the probes. Even at 50 MHz, you are not going to see a square wave. The rise and fall will be of a discernible width and the corners will be grossly rounded.

Something else that influences faithful reproduction of signal conditions is where the probe's ground is attached. I generally attach it as close as possible to the source of the signal in an effort to minimize reactive effects.
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Re: Timing for a multi-processor shared memory 65816 system

Post by AndrewP »

AndrewP wrote:
Your construction technique isn't great but it's not utterly horrible either.
:D

Yeah, I was talking to my cousin who is way more professional at the hardware stuff than me and he also came up with two major points. The first was that I probably need to put this on a PCB because there may be a problem with the soldering somewhere (amongst other problems with living on stripboard). I've gone over it with a magnifying glass (well my phone's camera) and, yeah... maybe it's good maybe it's not.
BigEd wrote:
One thing that might be worth trying is to feed this clock-like signal into a divider.
The second thing he mentioned is that my 200MHz scope running at 500MS/s is not going to be reading a square signal at 100MHz, and that it might be reading a much smaller voltage than truth. But putting this signal through a divider makes me believe there is something wrong. The green signal is ÷ 2 and the cyan signal is ÷ 4 and a 25MHz signal should be well within readability.

As this is all for curiosity's sake I'm going to two more clock oscillators, 5MHz and 25MHz as I have them knocking around.
BigDumbDinosaur wrote:
...I generally attach it as close as possible to the source of the signal in an effort to minimize reactive effects.
Thanks, I hadn't realised that. That wire at the back of the board that just connects ground to ground is what I was using to connect the probe's ground to. I'll retry with like that after I've checked the probe compensation you mentioned.

Thanks all!
- Andrew
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