1st design

[jzaun]

I'm trying out my hand at creates a 6502 system. Its a 6502, 3 VIAs, RAM and ROM. I was wondering if anyone would mind taking a look at it and seeing if I made any mistakes before I get a PCB made. Or really have any comments at all. I'm still learning all this and the most I've done so far is a much smaller breadboard setup.

I've attached the schematic as a PDF but I've also put it on on EasyEDA.

Thanks
- jzaun

[Dr Jefyll]

Hi, jzaun. Glad to hear about your project. But I guess you didn't see this recent thread:

Quote:

I'd be glad to help. But, honestly, I find it too laborious reading a schematic like this.

There are several fairly clear comments in the posts that follow. You should probably read them. Message is, you need a real schematic if you're hoping folks will volunteer their assistance.

I did notice one little thing. This capacitor isn't connected properly. Do I need to explain? Cheers,

Jeff

[jzaun]

Dr Jefyll wrote:

Hi, jzaun. Glad to hear about your project. But I guess you didn't see this recent thread:

Quote:

I'd be glad to help. But, honestly, I find it too laborious reading a schematic like this.

There are several fairly clear comments in the posts that follow. You should probably read them. Message is, you need a real schematic if you're hoping folks will volunteer their assistance.

Thanks, I'll read through that now.

[jzaun]

I've worked on sheet 1 based on the other thread I was pointed to. I've connected things directly rather than a bunch of netlists. But before I work on the other sheets, I'd like feedback on this one. Is this easier to follow? Are their ways to make it easier to understand or changes I should make to the layout?

Thanks for taking a look,
- Justin

[BigDumbDinosaur]

jzaun wrote:

I've worked on sheet 1 based on the other thread I was pointed to. I've connected things directly rather than a bunch of netlists. But before I work on the other sheets, I'd like feedback on this one. Is this easier to follow? Are their ways to make it easier to understand or changes I should make to the layout?

Thanks for taking a look,
- Justin

It seems there are missing connections in there. Or, is it in color?

[BigEd]

Welcome, Justin!

[jzaun]

BigDumbDinosaur wrote:

It seems there are missing connections in there. Or, is it in color?

Hi BigDumbDinosaur. Not sure how but the colors of some of the wire junctions went to red, I've verified on the EasyESD forum that the color is just a setting and doesn't mean anything. I've set the colors all to white.

BigEd wrote:

Welcome, Justin!

Hi BigEd. Thanks :)


I've updated the schematics to remove most netlists that are contained on the same sheet. The exception is the last sheet as I couldn't figure out a clean way to connect the display. The existing netlists are setup as inputs on the left and outputs on the right.

Any feedback on the schematic of the 6502 computer or on the schematic layout would be very welcome.

Thanks for looking,
-- Justin

[Dr Jefyll]

Justin, I think folks are a little busy at this time of year, and that's one reason you've had little response. But these schematics are much better!

The color scheme could still use improvement, IMO. I know you have to wrestle with EDA to control this, but it's probably worth the effort.

Meanwhile you're waiting for some design feedback! To speed things up I've reproduced your drawing in the style I (and many people) prefer.

-- Jeff

[BigDumbDinosaur]

What is the purpose of the CD4082? 4000-series logic is very slow, even at elevated voltages.

Also, it would be more informative if gates are drawn as gates, not boxes with pins. An AND gate drawn as an AND gate is much more informative than a collection of six AND gates in a rectangle. Try as I might, I just can't remember all the part numbers and what they do.

Something else I noticed is components don't have component IDs, such as R2 or U3. Was that an omission of oversight or intent?

[GARTHWILSON]

BigDumbDinosaur wrote:

What is the purpose of the CD4082? 4000-series logic is very slow, even at elevated voltages.

It's a dual 4-input AND gate. It wasn't in my NSC books, so I had to look it up online. Its max prop delay at 5V is 250ns! It should be ok of the IRQ\ ANDing, but Justin, for the EEPROM address decoding, if you ever go beyond 1MHz, you'll want to use at least 74HC logic. I know it will require two gates to replace the one, but the combined propagation will still be much, much faster.

Quote:

Also, it would be more informative if gates are drawn as gates, not boxes with pins. An AND gate drawn as an AND gate is much more informative than a collection of six AND gates in a rectangle. Try as I might, I just can't remember all the part numbers and what they do.

Justin, it will always be good to draw out the actual gates, rather than drawing rectangles with, in this case, A, B, C, D,... down the sides. I expanded the "General Steps For A Successful Project" page of the 6502 primer to add a section (actually now the entire last half of the page) on "Getting help on the 6502.org forum."

Dr Jefyll wrote:

To speed things up I've reproduced your drawing in the style I (and many people) prefer.

Thanks. I wasn't able to read the dark blue labels against the black background without getting up off my chair and getting really close to the monitor. It looked like there might be something there, but that was the extent of it, even though my vision is very clear.

Why are there two clock circuits with their outputs tied together? Are they just options to plug in two different sizes of packages, and only one will be there at a time? (Otherwise you definitely don't want two outputs fighting each other.)

On sheet 4, I strongly recommend putting at least a ground connection on the PORTA and PORTB connectors, if not also the +5V. Further, you could use dual-row pin headers (so you can plug standard-sized IDCs into them) and put ground pins on opposite corners, and Vcc pins on the remaining two opposite corners, so if something gets plugged in backwards, the power and ground will still be correct and you won't destroy anything. Standard IDC (insulation-displacement connectors, which you press onto ribbon cables) come in 10, 14, 16, 20, 26, 34, 40, and 50 connections.

Be sure to add debouncing to your reset circuit. The potential problem and remedy is described in the reset page of the 6502 primer. Be sure to go through the entire 6502 primer though. It was initially written about 20 years ago to address problems and questions that kept coming up on the forum, then I finally got my own site and got it posted in 2012, and I keep making improvements to it regularly. It's in 22 logically organized sections. It will save you a lot of grief.

I'd like to see comments about the USB keyboard circuit from anyone who has looked into USB more than I. I have a fat book about it, but have not looked in depth at the timing.

[AndrewP]

GARTHWILSON wrote:

BigDumbDinosaur wrote:

What is the purpose of the CD4082? 4000-series logic is very slow, even at elevated voltages.

It's a dual 4-input AND gate. It wasn't in my NSC books, so I had to look it up online. Its max prop delay at 5V is 250ns! It should be ok of the IRQ\ ANDing, but Justin, for the EEPROM address decoding, if you ever go beyond 1MHz, you'll want to use at least 74HC logic. I know it will require two gates to replace the one, but the combined propagation will still be much, much faster.

Getting a bit side-tracked but... if you need a 4-input AND gate then try a SN74F21DR or it's sibling the 4-input NAND gate SN74F20DR. If you're using a breadboard you'll need to solder them onto a SOP14 adapter first. They have typical propagation delays listed as 3.3ns. I have one chugging along at 65MHz quite happily.

Check your voltage levels though, I don't know if F plays nicely with HC. There's a gotcha if you're using it in a 3.3V setup but it looks like you're using 5V everywhere (for 3.3V the inputs can be 3.3V but the supply must be 5V to get at least a 2.4V high out).

[BigDumbDinosaur]

AndrewP wrote:

Getting a bit side-tracked but... if you need a 4-input AND gate then try a SN74F21DR or it's sibling the 4-input NAND gate SN74F20DR. If you're using a breadboard you'll need to solder them onto a SOP14 adapter first. They have typical propagation delays listed as 3.3ns. I have one chugging along at 65MHz quite happily.

74F logic is a power hog and performs no better, on average, than 74AC. I'm somewhat amazed that 74F devices are still available through distribution.

Quote:

Check your voltage levels though, I don't know if F plays nicely with HC.

74F has TTL-level outputs, so problems might ensue in attempting to drive 74HC. I absolutely do not recommend the use of 74F in new designs and would not even use 74F to repair old equipment that was built with it.

[AndrewP]

BigDumbDinosaur wrote:

74F logic is a power hog and performs no better, on average, than 74AC. I'm somewhat amazed that 74F devices are still available through distribution.

Gah! That would explain why my current draw is so high. I just cannot find other 4 input NAND / AND gates that interface with the LVC ICs I'm using.

[Dr Jefyll]

I'm not fond of the 74F series. But the chips are fast, and the family does offer certain gates/functions that're unavailable elsewhere. For me that's the only argument in favor of using a 74F chip. If I use 74F at all, it would be just a single chip or maybe two, certainly not the entire project.

Sometimes there's a specific problem to be solved, and no entirely comfortable answer. The rational approach is to list the pros and cons of using 74F, then assign a weight to each of those factors according to prevailing circumstances.

For example, if the project is to be battery operated then 74F's hunger for power weighs heavily against it, probably outweighing the appeal of the sought-after gate/function. An alternative can usually be found, awkward though the alternative may be. This too needs to be weighed.

In other circumstances, a few extra mA won't matter much, and the availability of a key function may tip the decision in 74F's favor. Been there, done that. Had to hold my nose, but it was the right decision.

-- Jeff

[BigDumbDinosaur]

AndrewP wrote:

BigDumbDinosaur wrote:

74F logic is a power hog and performs no better, on average, than 74AC. I'm somewhat amazed that 74F devices are still available through distribution.

Gah! That would explain why my current draw is so high. I just cannot find other 4 input NAND / AND gates that interface with the LVC ICs I'm using.

All 74AC devices will run at and accept 3.3 volt inputs.