POC COMPUTER VERSION TWO: A New Direction

[BigDumbDinosaur]

floobydust wrote:

Ouch! That hurts.... more fancy coasters for the workshop it seems.

Also, their straight edges make them good for drawing short lines.

J64C wrote:

Gotta post pics of the boards anyway though! Can’t leave us hanging.

I suppose. I'll see what I can do.

[jmthompson]

BigDumbDinosaur wrote:

The PCBs arrived on Monday, and as I was preparing to get the SMT stuff soldered in place, I discovered a major boo-boo in the layout. The board is electrically correct but the footprint I used for the 'AC245 transceiver was wrong. It has the right number of lands but is the wrong package width

Welcome to the club. On my first build, back in 2017, I picked the narrow (7mm) DIP footprint for my 6850 instead of the 15mm one. Fortunately I was able to rig up an adapter with some perf board, a socket, and some headers. Didn't even bother fixing that problem until I upgraded the design earlier this month.

[plasmo]

If it is any comfort, I'm the record holder of the biggest IC footprint mistake: That's a BIG 64-pin 68000 tilting about 45 degree to fit a 600 mil-wide footprint; correct footprint is 900 mil wide.
Bill

[BigEd]

Pythagoras to the rescue!

[Dr Jefyll]

plasmo wrote:

That's a BIG 64-pin 68000 tilting about 45 degree

Bill, I love the stubborn, "don't take no for an answer" attitude! More of your obstinate artistry in this thread...

-- Jeff

[barrym95838]

plasmo wrote:

If it is any comfort, I'm the record holder of the biggest IC footprint mistake: That's a BIG 64-pin 68000 tilting about 45 degree to fit a 600 mil-wide footprint; correct footprint is 900 mil wide.
Bill

I would just mount a tiny 5V fan at one end and call it extra cooling surface area.

[plasmo]

it is a different way to shrink the size of 64 DIP to save pcb real estate.

I also have a footprint error involving a 64-pin "Shrink DIP". There is nice photo of it somewhere...
Bill

Edit, here is the picture. Notice the row of 32 pins at the bottom of picture; it is not wide angle lens distortion.

[BigDumbDinosaur]

plasmo wrote:

If it is any comfort, I'm the record holder of the biggest IC footprint mistake: That's a BIG 64-pin 68000 tilting about 45 degree to fit a 600 mil-wide footprint; correct footprint is 900 mil wide.

Yikes! That looks downright dangerous. At least you were able to salvage the PCB and complete the assembly.

[Martin A]

plasmo wrote:

Notice the row of 32 pins at the bottom of picture; it is not wide angle lens distortion.

Would that be 1.87mm spacing instead of 1.78mm ???

[BigDumbDinosaur]

BigDumbDinosaur wrote:

The PCBs arrived on Monday, and as I was preparing to get the SMT stuff soldered in place, I discovered a major boo-boo in the layout...Supposedly, I'll have the new PCBs and stencil on Thursday.

The new boards and stencil arrived. The bus transceiver footprint is now correct. Time to build the contraption and see if she goes or blows.

[Martin A]

I had a chance to put the scope on the board I built based on the POC2 design.

Starting with the clock stretching, both 1 and 2 wait states appear to be inserted as expected. Seen here with 1 wait state selected.

longer shot of the wait states

The average frequency detected by the scope shows that particular section of code (probably keyboard scanning) has a 5 to 6% slowdown over all as the master clock is 20mhz for a nominal CPU speed of 10mhz. That's a small price to pay compared to running the board ad the speed of the slowest I/O component.

The first test runs were done with a slightly out of spec HC parts, both flip flops have been replaced with newly arrived AC parts and the clock from the flip flop shows a little ringing:

Scoping the clock side of the damping resistor

On the CPU side of the 120R resistor the ringing is gone, but the waveform is somewhat rounded:

CPU side of the damping resistor

Not that the CPU seems to mind, the rise and fall rate in the mid range is nice and fast.

[BigDumbDinosaur]

Martin A wrote:

On the CPU side of the 120R resistor the ringing is gone, but the waveform is somewhat rounded...

Looks as though your clock circuit has higher-than-average parasitic capacitance, or your probe is loading down the circuit.

[Martin A]

BigDumbDinosaur wrote:

Martin A wrote:

On the CPU side of the 120R resistor the ringing is gone, but the waveform is somewhat rounded...

Looks as though your clock circuit has higher-than-average parasitic capacitance, or your probe is loading down the circuit.

I wouldn't bet against either to be honest. The important thing is your design appears to be working as intended.

[BigDumbDinosaur]

J64C wrote:

Gotta post pics of the boards anyway though! Can’t leave us hanging.

Here's a pic of the bad board and the good board. The bottom board is the good one.

[BigDumbDinosaur]

BigDumbDinosaur wrote:

Quote:

The PCBs arrived on Monday, and as I was preparing to get the SMT stuff soldered in place, I discovered a major boo-boo in the layout...Supposedly, I'll have the new PCBs and stencil on Thursday.

The new boards and stencil arrived. The bus transceiver footprint is now correct. Time to build the contraption and see if she goes or blows.

Here are a few more pics.

POC V2.0 PCB Top Layer

POC V2.0 PCB Bottom Layer

POC V2.0 PCB w/SMT Components