Yes, agreed. If feasible this may be the preferred approach.

Yes, agreed. I’ll try to do that. Some good suggestions on process Dieter. Thank you.

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C74-6502 Website: https://c74project.com

Yes, ROM is out of the question. It’s a choice between using GALs or Decode RAM. The time-critical bit is to figure out the Addressing Mode of the opcode so we can know which registers are to be loaded into the next pipeline stage. I am using a 32-bit wide RAM for microcode and quickly running out of control bits. A second microcode RAM would tilt the decision since I will have lots of spare control bits there. I might as well use them for decoding the opcode. An advantage of using RAM is that it will then be much easier to accommodate alternate instruction-sets (more on that later).

Yes, agreed ... it’s on my To Do list.

Remember that this is a microinstruction pipeline so the issue does not arise. Self-modifying code is a real nuisance in an instruction pipeline, where the pipeline has to be flushed if self-modifying code is detected. For a more detailed description of a 6502 instruction pipeline, see this thread.. That design is a closer analogue to a traditional RISC pipeline, and self-modifying code was a problem (not only in the Dormann suite but also with FORTH and BASIC. I chose to add NOPs into the instruction stream manually rather than instrument the pipeline to detect self-modifying code).

Edit: Here is a relevant post on the thread that you might find interesting. It specifically discusses Self-Modifying Code (SMC).

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C74-6502 Website: https://c74project.com

I chose 7628 FR4 because I understand it is better suited to impedance controlled PCBs for exactly this reason. (As with everything else, though, it’s just something I read so I may be completely off-base ).

Great idea ... he might find a 100MHz TTL 6502 sufficiently “are-you-out-of-your-mind” crazy to be interesting!

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C74-6502 Website: https://c74project.com

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Microvias are typically depth limited. They can only go from outside layer to first inner layer, and that layer needs to be very thin. I've used them once time for a project (for small BGA with 0.4 mm pitch)

I suppose they could also go from inner to inner, if these are opposite sides of same physical board layer.

Thanks for this idea Arlet. (I had to ask Dr Jefyll to help me understand it but I get it now). There seem to be several good options for dealing with the dual-supply so I think I’ll stop worrying about it for now. Thanks!

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C74-6502 Website: https://c74project.com

Thanks for this good advice Garth. In fact, I don’t yet know whether or where we might see transmission lines in the layout. With luck I can keep the number of signal traces that require termination down to a minimum and be more cavalier with the rest.

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C74-6502 Website: https://c74project.com

If you choose to use a diode to drop the voltage, make sure you place your decoupling capacitors after the diode, near the 2.5V IC pin.

Rather than creating a detailed block diagram, I thought I might simply publish the Logisim file. It has the significant advantage of being already complete and accurate -- two important things that a detailed block diagram currently lacks!

For those that do not have Logisim, I have include here a png image which can be zoomed into to reveal all the CPU circuitry:
For those that do have Logisim, I am using Logisim "Evolution". When you load the C74-100 circuit file, you will be greeted by the following:
To set the CPU running the Dormann Test Suite:

1. Right click on the RAM module and select "Load Memory Image"
2. Load the file "Test_6502_RAM_Image" included in the attached zip file
3. Set the RDY and BE pins to "1"
4. Start the clock
5. Press the "RES" button.

The Dormann test suite will begin to execute. You can then navigate to the "6502" module to watch the CPU execution up close. Of course you can also type your own program into RAM, point the RESET vector in high memory to it and press the RES button.

You will find the following files the attached zip file:

• C74-100 Critical Path (V1).pdf -- a detailed listing of all signal paths through the CPU with estimated tpd
• C74-100 Decoder Values (V1).pdf -- a table showing the encoding used for both microinstruction and instruction decoding
• C74-100 V1.circ -- the Logisim file
• Test_6502_RAM_Image

Disclaimer: Please consider all this material in draft form and subject to change without notice. The main objective for this model is to test out the ideas. As such, implementation details may differ materially from what is contained herein.

As always, I would be happy to answer any questions or provide any additional explanations.

Cheers for now,
Drass

EDIT: Added link to Logisim Evolution

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C74-6502 Website: https://c74project.com

Hi Drass,

It looks very professionaly done and works very well.

Maybe it needs to be clarified that this is intended to run on Kevin Wash "Logisim Evolution" fork, a.k.a Logisim Holy Cross Edition; unless I am using a wrong version, it actually does not load on the mainstream reds-heig version. Just in case you were not aware of it, the Holy Cross edition also features the File Viewer component, which when properly formatted, allows you to visually display the assembly source file, with the currently fetched instruction highlighted. I really love that.

From your simulation I learned that it is a lot more effective (read faster) to just build the model out of native logisim components, than attempting to emulate 74xx ics down to logic gates as I've been doing so far. Btw, I like the D.IN, D.OUT trick to get memory out of the 6502 subcircuit.

Definitely, but you do need to keep the 7400 series ICs in mind as well. In this case I’ve marked various Logisim components with the 7400 series equivalents I intend to use. I’m also careful to reflect the correct pinouts. For example, I put inverters in front of inputs which I know are active-low on the 7400 series ICs but are active-high in Logisim. That keeps the logic straight from the start.

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C74-6502 Website: https://c74project.com

yes, I saw that. Since I already had many 74xx ics modelled in sub circuit boxes I just have now replaced their down-to-logical-gates implementations by native logisim components at the bottom level, and it’s definitely much faster. The the same higher level boxes still remain though. That makes the model look closer to the schematic in general, but it looses the sense of digital diagram that you get by using the native components right at the top level.

Btw, I don’t quite get how you perform the sbc function in the model. That should require the negation of one of the ALU inputs and I was curious about how that would add to the FET adder propagation delay. I’ve been looking for XOR gates at one of the ALU inputs but I can’t see them. Please can you elaborate on this?

It’s pipelined. The operand is inverted in the prior cycle. If you look toward the bottom of the Register File you will see two paths from DB to the ALUB input bus. One has an inverter on it and the other does not. SBC loads the inverted operand into ALUB whereas ADC loads the operand as is. The ALU itself does a simple ADD in either case.

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C74-6502 Website: https://c74project.com

Nice. You end up with something closer to a schematic then, which is wise. I expect you minimize transcription errors when finally making schematics. (The C74-6502 had a couple of such errors which required patching the PCBs as a result. It’s much too easy to make these mistakes when you’re dealing with thousands of connections. The whole thing might have been avoided with your approach).

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C74-6502 Website: https://c74project.com