I mentioned in another topic that I was building a
retro 6502 computer. BigEd suggested I share, so here goes.
I am in the process of bootstrapping a modular 6502 system built around the open source Z50 bus. So far I have assembled a third party
backplane and designed several boards to plug into it, currently CPU, memory, serial and prototype boards. Boards are either 100x100mm, CPU and prototype, or 100x75mm, serial and memory.
The CPU card contains a WDC65C02 processor, clock generator (1MHz), address and data bus buffers and an ATF22V10 GAL for utility and memory decode. The original design was for NMOS, hence the buffers, but it turns out the second hand chips I obtained from China were all defective in various ways. After a several frustrating debug sessions I decided to buy a couple of new processors. It paid off, the board worked almost immediately. I say almost as I hadn't realised the BE and VPB mods in the new model.
The memory board is designed for 2 x 32k SRAMs and 1 x 32k ROM. I've made the design quite flexible, the memory map is configurable using DIP switches. You get to choose your RAM/ROM sizes - 32/32, 40/24, 48/16 or 56/8. I am using a second GAL, an ATF16V8, for the chip select function.
The serial card has a single 6551 type chip. Because of the Chinese chips problems I decided to get a WDC65C51, not realising it has its own issues. I intend to proceed with the NMOS for now and see how it pans out.
One of the prototype cards has been set up as a static debug board. I've taken the Mostek example circuit from the hardware manual (pg. 125) and put it into an old Xilinx XC9536 CPLD. I happened to have a few lying around from a previous project and they are both 5V powered and 5V tolerant. It's very much a work in progress but the halt/run/single step operates properly. What is missing is an address/data bus display.
Toolwise I am using the cc65 project, just the assembler and linker portions for now. I'm happily building test ROM's from the command line using Gnu make.
Best I can tell the CPU and ROM are working properly. I've based my memory map on the Apple ][, so RAM 0000-7FFF, IO C000-CFFF and ROM E000-FFFF. The first test ROM just has the reset vector jump to F800 and then access a bunch of IO memory locations in a tight loop. From what I can see on the 'scope it's running true and generating the expected memory enable signals.
This weekend my plan is to add the serial card to the mix and try for "Hello world". Once that is working I'll aim at a workable console so I can start on RAM testing and then on to a basic ROM monitor.
All good fun.