On another subject, the sad truth is that increasing numbers of modern 5 volt CMOS devices (example: many RAMs, and at least one CPLD I'm aware of)
do not produce rail-to-rail voltage swings on their outputs. The logic high falls short of Vcc (even short of a valid CMOS logic high, as BDD noted).
That may seem absurd -- after all, the C in CMOS means
complementary! But the effect is as if the chip's internal Vcc is somewhat lower than the +5 that arrives from the outside world. And indeed that may actually be the case.
Somewhere (here on this forum?) I heard an explanation which seems plausible although I can't verify it. Modern geometries are smaller than those used in legacy 5 volt stuff, and smaller translates to more cost-effective for the manufacturer. But modern geometries are also low voltage, 3.3 volt for instance. So, nowadays manufacturers are in some cases supplying the 5V market with chips that operate at a lower supply voltage internally. It's trivially easy to make the
inputs 5-volt tolerant. The outside world won't "notice" this aspect of low-voltage operation. But with
outputs it's a different story.
Does anyone have authoritative details on this? The datasheets don't explain reasons, of course. But they
do tell us not to expect symmetrical (ie, rail-to-rail) voltage swings on the outputs.
-- Jeff
_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html