I have the Eyes/Lichty manual in hardcopy now. It says absolutely no such thing.

However, I *have* managed to unearth a WDC datasheet dated 1991, which *does* say so, as an erratum right at the end. I've attached a copy.

Also, note on page 23 the VIL and VIH ratings for the '816. Recall my theory that the current data sheet is wrong and the '816 (and 'C02) must have TTL-compatible inputs in order to work with the currently-available 5 volt SRAM?

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

If the SRAM has CMOS output drivers, it'll have no problem satisfying CMOS-style input thresholds.

I suspect that the modern WDC parts can also work with TTL inputs if they are put in a TTL system - and people *have* put a W65C02S in, for example a BBC Micro, with 74LS glue logic everywhere - but that timing margins are significantly worse in that case. In a 2MHz BBC Micro running at 5V, that's not noticeable.

One really amusing note is that the older datasheet lists the '816 and '802 as working down to as little as 1.2V, but only at 40kHz. Perfect for running off a single cell and a watch crystal. Someone should try that with the modern parts.

I too am skeptical. Try as I might, I see nothing in the test code that would conclusively prove the device under test is a genuine '816.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

The two SRAMs I've used are specified to produce TTL output levels. Manual testing confirmed that. They pull up to near three volts, but that is still more than a half volt shy of a valid CMOS logic 1 level.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Definitely. Most of the older design CMOS devices quote specs for TTL environment loads, as this was the expected environment at the time of design. This might have some folk believe they won't meet more up to date CMOS input specs. However, under CMOS environment loads they will perform just fine. Indeed, as you mention, this is to be expected.

I've put WDC 65C02s into an OSI 600 (Superboard II), a SYM-1 and an Apple IIe and they all worked just fine. In fact the bus signals never looked so good.

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Bill

The 74xCT245 (74HCT245, 74ACT245, etc.) between the '816 and the system data bus make the thresholds irrelevant, as memory and other devices on the bus don't feed the '816 directly. The '245 is there to prevent bus contention with A16-A23 going into the '573, not give the '816 any additional drive strength (since it doesn't need any help anyway).

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Interesting to score some '816 parts. It's worth noting that out-of-spec, failed, or rather old parts could turn up on these markets. If it seems to work in a given application, that sounds good to me. If it then fails to work in some other application, I wouldn't be too surprised. Don't go building medical equipment from such sources!

It is of course wrong to expect to get pristine chips from such sources, but I don't suppose anyone is expecting that. If you're inclined to want the genuine article, you know that you need to pay full price from a reputable channel.

I don't know of any other 65xx chip which outputs VPB, VDA and VPA signals, and without these it would not be possible to decode the cycle type info. The CPU type determination routine executes opcode 47 as EOR [x]. I tried the mode switching code and it works.
The screens below show EOR [83] and mode switching (see EMX letters changing case) with 24-bit addresses and 16-bit data. Hope this will convince you.

Another interesting point: the X mode output changes during the fetch of the next instruction after REP, so even if the CPU is already switched to 24-bit addressing, it doesn't say so. M output changes during the last cycle of REP - correctly. NOPs following mode switch seem to be a good idea regardless of timing issues.

And no, I will definitely NOT design any medical equipment using any 65xx.

One could simply put a scope on pin-3. If it's any kind of 6502 you'd see a clock signal there. If it's a 65816 you won't.

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Bill

That would depend upon which package is being used. Pin 3's assignment is different in each case.


The firmware code in my POC V1.1 unit is peppered with REPs and SEPs that are immediately followed by regular instructions, not NOPs. I've never had any issues with mode switches, even at 15 MHz. Whatever timing errata my have existed in the past with REP and SEP seems to have been eliminated.


Funny you mention that. Years ago, Dell computers had an unusually high hard drive failure rate, with quite a few barely making it past the one year warranty period. It turned out Dell had been purchasing drives from manufacturers that had rejected product due to the drives not formatting to rated capacity due to magnetic media defects. So the (relabeled) drives were being reformatted to lower capacities, marked as such and dumped on the "secondary" market at a fraction of the going price. Dell, seeing an opportunity to improve sales margin on their product, bought a large number of these drives and screwed their customers in the process.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Okay, question for my own purposes: is there a difference in the behaviour of the MX signal between the old 65816 and the current one? Running the same code sequence on a genuine current '816 and carefully sampling the signal should answer that question. It's a test I can incorporate into the 6502 Fake Finder, if there is indeed a detectable difference.

Quite true.

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Bill

gbm, I'm a little uncertain, and other may be, too. You seem to imply that the screen shots you posted reveal info based on signals from a real, physical '816... but you didn't actually say so (and the line up top about "Software-Defined Computer" confuses the matter by sounding like a simulation instead). Can you be explicit please regarding all the details of what's in the scree shots? Thanks.

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

On another subject, the sad truth is that increasing numbers of modern 5 volt CMOS devices (example: many RAMs, and at least one CPLD I'm aware of) do not produce rail-to-rail voltage swings on their outputs. The logic high falls short of Vcc (even short of a valid CMOS logic high, as BDD noted).

That may seem absurd -- after all, the C in CMOS means complementary! But the effect is as if the chip's internal Vcc is somewhat lower than the +5 that arrives from the outside world. And indeed that may actually be the case.

Somewhere (here on this forum?) I heard an explanation which seems plausible although I can't verify it. Modern geometries are smaller than those used in legacy 5 volt stuff, and smaller translates to more cost-effective for the manufacturer. But modern geometries are also low voltage, 3.3 volt for instance. So, nowadays manufacturers are in some cases supplying the 5V market with chips that operate at a lower supply voltage internally. It's trivially easy to make the inputs 5-volt tolerant. The outside world won't "notice" this aspect of low-voltage operation. But with outputs it's a different story.

Does anyone have authoritative details on this? The datasheets don't explain reasons, of course. But they do tell us not to expect symmetrical (ie, rail-to-rail) voltage swings on the outputs.

-- Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html