This one really has me scratching my head.
This is a different design than before. A much simpler and smaller system with a different intent. It kind of go it's start with a discussion on these boards about a minimal system for running EhBASIC and morphed into a minimal but versatile system. In any case, I'll get into more detail on that when I can get this thing running with the W65C02.
Here is the behavior. It runs absolutely fine with and NMOS or old Rockwell CMOS CPU. In fact, it behaves well over clocked with either of those.
With the W65C02 (for which I implemented the 'lessons learned' from the previous project) it sort of works. It will boot and run the EhBASIC initialization to the READY prompt. From there I can load or enter and edit programs. It will execute the LIST command with or without arguments and it will execute the PRINT command, but only without arguments.
I have tried different ways to select RAM (with and without a short delay on A15) as well as different ways to implement /OE on both the RAM and ROM chips (tied to ground, tied to /CE or tied to !R/WR [inverted R/WR]) to no avail. Delaying the A15 line for RAM select make matter worse. The other changes make no difference.
Any help would be appreciated.
Here is the schematic:
Here is the CUPL Code:
Code: Select all
/* *************** INPUT PINS *********************/
PIN 1 = XTL_1 ; /*XTAL */
PIN 2 = A14 ; /* */
PIN 3 = A15 ; /* */
PIN 4 = A13 ; /* */
PIN 5 = A12 ; /* */
PIN 6 = A11 ; /* */
PIN 7 = A10 ; /* */
PIN 8 = RW ; /* */
PIN 9 = A9 ; /* */
PIN 10 = A8 ; /* */
PIN 11 = Phi2 ; /* */
PIN 13 = D3SEL ; /* */
/* *************** OUTPUT PINS ********************/
PIN 14 = R ; /*Low=Read, High= Write !(R/W) */
PIN 15 = DD ; /*Data Direction - off-board expansion buffer */
PIN 16 = DEV_1 ; /*Device select 1 - active low */
PIN 17 = ROM_CE ; /*ROM Select - active low */
PIN 18 = DEV_2 ; /*Device select 2 - active low */
PIN 19 = DEV_3 ; /*Device select 3 - selectable */
PIN 20 = DEV_0 ; /*Device select 0 - active low */
PIN 21 = RQW ; /*High=Read, Low=Phi-2 qualified write*/
PIN 22 = OND ; /*Oscillator node*/
PIN 23 = XTL_2 ; /*XTAL and oscillator out*/
/* Intermediate values */
a = A10 # A11 # A12 # A13 # A14;
b = !A15 # a; /* Low = valid I/O address */
d3 = b # !A8 # !A9;
/* Output definitions */
R = !RW;
DD = !b & RW & (A8 # A9); /* High = read from expansion bus I/O. Low all other times */
RQW = !(Phi2 & !RW);
ROM_CE = !A15 # !a;
DEV_0 = b # A8 # A9;
DEV_1 = b # !A8 # A9;
DEV_2 = b # A8 # !A9;
DEV_3 = D3SEL & d3 # !D3SEL & !d3;
OND = !XTL_1;
XTL_2 = !OND;Here are I/O timings. The traces are as follows: Yellow=Phi2 (system clock), Blue= I/O CE, Red=qualified R/W, Green=DB
I/O Read using the Rockwell:
The following are ROM Read timings. The traces are as follows: Yellow=Phi2 (system clock), Blue= ROM CE, Red=/OE, Green=DB
For the Rockwell:
The following are RAM read timings. The traces are as follows: Yellow=Phi2 (system clock), Blue= RAM CE, Red=/OE, Green=DB
For the Rockwell:
The following are RAM Write timings. The traces are as follows: Yellow=Phi2 (system clock), Blue= RAM CE, Red=Qualified R/W, Green=DB
For the Rockwell:
This is an additional view of the WDC RAM Write timing. The traces are as follows: Yellow=/OE, Blue= RAM CE, Red=Qualified R/W, Green=DB
