Shadowing ROM into RAM?

[LIV2]

Hi

I have been thinking about speeding things up on my 6502 by copying the ROM to RAM at boot. I'm going to be using a CPLD for the glue logic so presumably this should make it easy
My plan is to have the ROM and RAM mapped to the same range (E000-FFFF) but have the RAM only selected for writes
Once the copy is done I will disable the ROM completely and enable reads from the RAM

The writing part is easy since I can have the address decoder select both the ram and rom at the same time. since the ROMs /WE is tied high it won't do anything with the writes
For reads though would I probably need to gate the ram's /CS so that it is only selected when either RW = 0 or the ROM is disabled by the CPLD i.e something like

Code: Select all

RAM2CS <= '0' WHEN (((to_integer(addr (15 downto 8) >= 16#E0#) AND (ROMEN = '0' OR RWB = '0'))

Does this make sense?
Will RWB be valid before PHI2 rises?

The RAM I'm using is Cypress CY7C199CN 15NS and my CPU will be running at 5MHz

[Alarm Siren]

R/W transitions at around 35ns after PHI2's falling edge, so yes it is valid before PHI2 rises.

[GaBuZoMeu]

If you assert /CSram, /WRram, /CSrom, and /OErom simultaneously the RAM will store the information coming out of the ROM during this read cycle. So you just need to read all ROM. Then you only need a mechanism to disable ROM access to further access RAM only. This could be a flip-flop reseted by /RES and set by the first RAM write within the address range of the ROM. You may also use an unused port pin.

[LIV2]

Alarm Siren wrote:

R/W transitions at around 35ns after PHI2's falling edge, so yes it is valid before PHI2 rises.

Awesome thanks!

GaBuZoMeu wrote:

If you assert /CSram, /WRram, /CSrom, and /OErom simultaneously the RAM will store the information coming out of the ROM during this read cycle. So you just need to read all ROM. Then you only need a mechanism to disable ROM access to further access RAM only. This could be a flip-flop reseted by /RES and set by the first RAM write within the address range of the ROM. You may also use an unused port pin.

This is an excellent idea and would make the process a whole lot faster. I look forward to trying it!

[GARTHWILSON]

Initially you said you wanted to speed things up on your 6502 by copying the ROM to RAM at boot. How are you planning to kick the clock speed up after the copying?

[BigDumbDinosaur]

GARTHWILSON wrote:

Initially you said you wanted to speed things up on your 6502 by copying the ROM to RAM at boot. How are you planning to kick the clock speed up after the copying?

That's a good question. Either the machine has to be clocked at a slower rate to accommodate the ROM, followed by a speed-up, or wait-states have to be used. The latter would be less tricky to implement, as glitching during a clock speed change might be a problem.

[LIV2]

Yep the plan is to wait state the ROM using RDY with a flip flop essentially like this post here: viewtopic.php?p=12661#p12661

The intention is to hopefully hit 10 MHz, at 5 MHz the waitstate isn't even needed and the ROM keeps up fine

[whartung]

BigDumbDinosaur wrote:

GARTHWILSON wrote:

Initially you said you wanted to speed things up on your 6502 by copying the ROM to RAM at boot. How are you planning to kick the clock speed up after the copying?

That's a good question. Either the machine has to be clocked at a slower rate to accommodate the ROM, followed by a speed-up, or wait-states have to be used. The latter would be less tricky to implement, as glitching during a clock speed change might be a problem.

I was going to suggest looking at the WDC boards to see how they do it, but turns out I was thinking of a feature built in to the W65C265S.

The W65C265SXB board has both a 32Khz Crystal and a 3.6MHz crystal, and the MCU has inputs for both, and an output, PHI2, to connect to other parts on the board. Flipping a bit in a control register tells the CPU which clock to use.

From the data sheet:

Quote:

PHI2 output is the main system clock used by the microprocessor for instruction timing, general on-chip memory, and I/O timing. The PHI2 clock source is either CLK or FCLK depending on the value of System Speed Control Register bit 1 (SSCR1). When SSCR1=0, then CLK is the PHI2 clock source. When SSCR1=1, then FCLK is the PHI2 clock source.

[LIV2]

Looking at the datasheet for the CY7199CN RAM I can see that you can assert /WE and /OE at the same time but the waveform doesn't seem to specify any particular timing requirements for this.
Has anyone got any experience with this? the datasheet implies that it doesn't care about /OE while /WE is asserted so I'm hoping asserting them both at the same time will be fine

If it works I can just assert /MWR at the same time as /MRD when romcs goes low and this should write to the RAM, loop through reading the whole ROM and then disable the ROM and I should be fine yeah?

I was thinking something like:

Code: Select all

RAMCS2 <= '0' when (to_integer(addr (15 downto 8)) >= 16#E0#) else '1';
ROMCS  <= '0' when ((to_integer(addr (15 downto 8)) >= 16#E0#) AND ROMEN = '0') else '1';

MRD <= RWB NAND PHI2;
--- If the ROM is selected and enabled, write the data to RAM2
--- Otherwise if the ROM is disabled only bring /MWR low on writes
MWR <= (RWB NAND ROMCS) NAND PHI2;

[BitWise]

LIV2 wrote:

Looking at the datasheet for the CY7199CN RAM I can see that you can assert /WE and /OE at the same time but the waveform doesn't seem to specify any particular timing requirements for this.

Its common in SRAM chips for /WE to override /OE. My quick and dirty 128K SRAM upgrade for the 265SXB does this as it has no additional glue logic.
https://tydbit.blogspot.co.uk/2015/12/i ... iting.html
My bigger 1M SRAM card has a PAL and produces /OE and /WE signals qualified with PHI2.

[LIV2]

Awesome thanks everyone

[BillO]

There should be no issue in asserting /WE while /OE is asserted. I am not aware of a SRAM chip where this would be a problem. If there is only one RAM chip on your board and you are not short on power at all, just tie /CE to ground and select your SRAM using a signal to /OE. This really reduces the power supply noise by leaving the SRAM powered on at all times and the propagation form asserting /OE to valid output is much faster than from asserting /CE or both /CE and /OE. OF course, make sure /WE is Phi-2 qualified.

[PaulF]

If you want to switch the CPU clock speed cleanly, have a look at this article: http://6502.org/mini-projects/clock-swi ... ching.html

It shows how to switch between two clock speeds without creating glitches.

[GARTHWILSON]

There's also this simpler clock-stretching one: viewtopic.php?p=11796#p11796

[kakemoms]

Please note that if using fast SRAM you need to have fast clock switching. If your clock switches slowly, it may generate confusion in the transition area. I have seen this when interfacing to older 1MHz 6502 systems with fast SRAM (50ns or faster).

A common fix for such is a schmitt trigger. Here is an article describing the problem&fix.