More Information

[muchtolearn]

I am at the stage where I need more information not just about the CPU
but how the architecutre works and fits all together. I am finding
random docs on line like datasheets for the CPU but that only
contains a portion of what I want to know.

Then I came across this:

http://uisprocesadores2008.wdfiles.com/ ... LMDch6.pdf

This is brilliant!!!
Except it is for the PC and the 8086.
Are there books like this for the 6502?

[GARTHWILSON]

There's the 6502 primer, about building your own computer, at http://wilsonminesco.com/6502primer/ . It has 22 chapters, or web pages, arranged in a logical order, with some of them being applicable to other processors as well, for example the one about displays, or the one about wire-wrapping. Many others are specific to the '02. It does assume a little background knowledge, like basic logic ICs and binary and hexadecimal number bases.

A very old 6502 hardware manual but probably still quite useful is the MOS Hardware Manual at http://wdc65xx.com/wp-content/uploads/2 ... _Jan76.pdf, on WDC's site. The software manual they have is, IMO, the best: "Programming the 65816 including the 6502, 65C02, and 65802" by David Eyes and Ron Liechty, at http://wdc65xx.com/Programming-Manual/ .

Check out the book list on this site, at http://6502.org/books, and other resources under the categories listed at the front page, http://6502.org/ .

For books about individual computer brands, I have links to loads and loads on my links page at http://wilsonminesco.com/links.html#brands . Elsewhere on the same page there are links to a lot of other valuable materials, and to others' 6502 websites, for example Rich Cini's website where he has posted scans of literally hundreds of 6502 books and documents. There are hundreds of links on my links page, mostly for 6502.

[muchtolearn]

I am interested in specifics of CPU. (ALU how it works with the
buses and R/W cycles). I need the technical information explained
and not just presented which I find alot of the 6502 books do.

[GARTHWILSON]

See Dieter's pages on this site, indexed at http://6502.org/users/dieter/ . He delves into ALU design.

[BigEd]

Hey muchtolearn, I see you've been here a while, but no-one has welcomed you. Welcome!

That first PDF you posted looks pretty general to me - it might use x86 as an example, but the information is general. There are three differences, off the top of my head, of the 6502 vs the x86 or Z80 world:
- the 6502 has a RnW output, instead of having separate read and write strobes. Therefore every bus cycle is either a read or a write. Later 6502-family offerings had pins to signal valid data accesses and valid program accesses, which means the system can distinguish bus cycles where the 6502 is not making an access.
- the 6502 is clocked at memory speed, whereas the x86 and z80, AIUI, take several clock cycles for one memory access.
- the 6502 has a single address space, so I/O devices share space with RAM and ROM. The x86 and z80 machines have a separate I/O space, which means they can have a full 64k of memory and simpler decoding.

Perhaps another difference is that DMA is common in the 8-world, not so common in the 6502 world.

[muchtolearn]

Big Ed
Thanks for the welcome!
Buses are a mystery to me can
You explain more/give definitions.
6502 only has 1 pin for R/W how
Is this done?

And I have completely different
Question about assembly language.
Why do JSR's need a RTS? If you
Have a JSR in your code the processor
Goes to this routine, executes it
And then goes back to the next line
After the JSR. the subroutine had been
Executed. So why do you need to put
A RTS. What to return to the subroutine
You have just executed? that does
Not make sense.

[GARTHWILSON]

muchtolearn wrote:

Buses are a mystery to me can You explain more/give definitions.

"Bus" usually means it goes to multiple things that take turns talking. Many things connected on the same line(s) can listen as once, but only one at a time talks. The major example is the data bus. The processor is on it, various memory ICs are on it, I/O ICs, and maybe other things too. All of these receive data at times, and put data on the bus at other times. The address bus goes to many things too; but in a simple system, only the processor puts addresses on it. In a more complex system, DMA (direct memory access, controlled by a DMA controller instead of the processor) may take control of it at times, or maybe something else I'm forgetting.

Quote:

6502 only has 1 pin for R/W. How is this done?

The phase-2 clock signal is the other part of that. "Read" is when R/W is high and phase 2 is high. "Write" is when R/W is low and phase 2 is high. Neither is happening when phase 2 is low, regardless of the state of R/W. This is covered toward the end of the clock-generation page of the 6502 primer I linked to above.

Quote:

And I have completely different question about assembly language. Why do JSR's need a RTS? If you Have a JSR in your code, the processor goes to this routine, executes it, and then goes back to the next line after the JSR. The subroutine had been executed. So why do you need to put A RTS? What to return to the subroutine You have just executed? That does Not make sense.

This is explained in the subroutine-return page of the 6502 stacks treatise, at http://wilsonminesco.com/stacks/sub_ret.html .

[DerTrueForce]

[Garth posted as I was writing this, but I'm going to put it here anyway]

The 6502 has only one signal for indicating a read or a write. This is not the only thing that's used for indicating an access, though. If the clock signal is low, the 6502 is not looking at the bus. This fact can be used to generate z80-style /RD and /WR signals for where that's necessary. 65-series peripheral ICs do that internally.

RTS exists to mark the end of a subroutine.
The 6502 executes instructions in roughly this order:

Code: Select all

<code leading up to subroutine>
JSR
<subroutine>
RTS
<code right after JSR>

I think it's a poor choice of mnemonic, because it suggests something like "Return To Subroutine". According to WDC, it actually stands for "ReTurn from Subroutine", which is highly counter-intuitive. I think of it as "Return To Sender". Same goes for RTI("ReTurn from Interrupt"), which I think of as "Return To Interrupted".

[muchtolearn]

This is great stuff!!
Thanks for the replies and answers.

so basically the RTS operand is used
Push and pull the JSR address onto the stack,
Correct?

I have some more questions.
address bus- information transfers takes
Place in one direction. From the CPU
To memory. (correct?)

Now please comment, correct discuss etc

When a CPU wants to transfer information
Between itself and a certain memory location,
It generates the 16 but address from an internal
Register on its 16 address pins, which then
Appears on the address bus. These 16 address
Bits are decided to determine the desired memory
Location. The decoding process normally requires
Hardware (decoder). Does this happen for
The 6502? What are the decodes?

[GARTHWILSON]

muchtolearn wrote:

so basically the RTS operand is used [to] push and pull the JSR address onto the stack, correct?

RTS is used by the subroutine to pull the return address off the stack and get back to the place it was called. RTS does not push anything, only pull the return address off and use it to know where to go back to.

Quote:

I have some more questions.
address bus- information transfers takes
Place in one direction. From the CPU
To memory. (correct?)

Yes, to memory but also to I/O ICs. The 6502 uses memory-mapped I/O. If you store a value to an address, the processor doesn't care what's at that address. You could be storing a value to a variable, or sending a byte out an output port, setting up a timer in an I/O IC, etc..

Quote:

Now please comment, correct discuss etc

When a CPU wants to transfer information
Between itself and a certain memory location,
It generates the 16 but address from an internal
Register on its 16 address pins, which then
Appears on the address bus. These 16 address
Bits are decided to determine the desired memory
Location. The decoding process normally requires
Hardware (decoder). Does this happen for
The 6502? What are the decodes?

Each device having more than one location (which means almost all devices) has internal decoding to select the right register within that device; so the only decoding that remains for you to do in your design is to have the logic to select the right device. This is explained in the address decoding page of the 6502 primer.

[muchtolearn]

yes correction. the JSR pushes the address
Of the JSR onto the stack and the RTS pulls
The address off the stack.

as for the answer you gave in the 2nd
Part it is confusing. can you please
Explain within a computer. I am
Only concerning myself at this
Stage to the motherboard and no other
Devices or peripherals.

[GARTHWILSON]

muchtolearn wrote:

yes correction. the JSR pushes the address of the JSR onto the stack and the RTS pulls the address off the stack.

The JSR pushes the address of the last byte of the JSR instruction. RTS takes it back off and increments it by one to get the address to jump to.

RTS, RTI, and JSR can also be used for other things besides the obvious, as discussed in section 11 of the 6502 treatise on stacks (stacks plural, including virtual stacks, not just the page-1 hardware stack).

Quote:

as for the answer you gave in the 2nd part it is confusing. can you please explain within a computer. I am only concerning myself at this stage to the motherboard and no other devices or peripherals.

The I/O ICs I was talking about are indeed usually on the motherboard. On my workbench computer for example (whose address decoding is the same as what's in the first diagram on the address-decoding page of the 6502 primer, in about the middle of the page), the first VIA (versatile interface adapter IC) is addressed at addresses $6000 to $600F. I have five more I/O ICs too. RAM appears at addresses 0 to $3FFF, and ROM from addresses $8000 to $FFFF. On this VIA IC, the addresses are:

Code: Select all

VIA:    EQU  $6000    ; The base address of the 6522 Versatile Interface Adapter is $6000.
PB:     EQU  VIA      ; Its port B is at that address.
PA:     EQU  VIA+1    ; Its port A is at address $6001.
DDRB:   EQU  VIA+2    ; Its data-direction register for port B is at $6002.
DDRA:   EQU  VIA+3    ; Its data-direction register for port A is at $6003.
T2CL:   EQU  VIA+8    ; Its timer-2 counter's low  byte is at $6008.
T2CH:   EQU  VIA+9    ; Its timer-2 counter's high byte is at $6009.
SR:     EQU  VIA+10   ; The shift register is at $600A.
ACR:    EQU  VIA+11   ; The auxiliary  control register is at $600B.
PCR:    EQU  VIA+12   ; The peripheral control register is at $600C.
IFR:    EQU  VIA+13   ; The interrupt  flag  register is at $600D.
IER:    EQU  VIA+14   ; The interrupt enable register is at $600E.

(The address $600F is the same as $6001 except that handshaking on the CA1 and CA2 lines was forced off even if you had it selected in the PCR at address $600C.) The computer's address decoding only has to select the VIA (or other IC) at the desired address. The selection of the individual registers within the VIA is handled internally to the VIA itself. It has four address-line inputs to pick one of 16 addresses there once the chip-select inputs are true. The four address-line inputs are typically connected to A0 through A3 of the system's address bus.

[muchtolearn]

The computer I use does not have ports.

Anyway, I went to your website and went to the page
on address decoding.

In fact, the Apple II did two memory accesses per cycle, two million per second at 1MHz, with the video accessing the memory during the first half of Φ2, and the processor during the second half, interleaving, so both could access the same memory at the same time at full speed, with no conflicts.

Where does this information come from? (Or can you explain this
in detail).

[DerTrueForce]

What computer is that, then? A computer with no I/O sounds awfully limited.

The reason the Apple II did two memory accesses per cycle is because the video circuitry accessed the RAM when the 6502 wasn't looking at the bus. The 6502 doesn't access the memory while the clock signal (Φ2) is high, so if the Bus Enable pin is used to tri-state the 6502's outputs, something else(in this case, the video circuitry) can access the memory if everything is fast enough.

[muchtolearn]

The reason the Apple II did two memory accesses per cycle is because the video circuitry accessed the RAM when the 6502 wasn't looking at the bus. The 6502 doesn't access the memory while the clock signal (Φ2) is high, so if the Bus Enable pin is used to tri-state the 6502's outputs, something else(in this case, the video circuitry) can access the memory if everything is fast enough.

And this information comes from where exactly?