muchtolearn wrote:
yes correction. the JSR pushes the address of the JSR onto the stack and the RTS pulls the address off the stack.
The JSR pushes the address of the last byte of the JSR instruction. RTS takes it back off and increments it by one to get the address to jump to.
RTS, RTI, and JSR can also be used for other things besides the obvious, as discussed in
section 11 of the 6502 treatise on stacks (stacks plural, including virtual stacks, not just the page-1 hardware stack).
Quote:
as for the answer you gave in the 2nd part it is confusing. can you please explain within a computer. I am only concerning myself at this stage to the motherboard and no other devices or peripherals.
The I/O ICs I was talking about are indeed usually on the motherboard. On my
workbench computer for example (whose address decoding is the same as what's in the first diagram on the
address-decoding page of the 6502 primer, in about the middle of the page), the first VIA (versatile interface adapter IC) is addressed at addresses $6000 to $600F. I have five more I/O ICs too. RAM appears at addresses 0 to $3FFF, and ROM from addresses $8000 to $FFFF. On this VIA IC, the addresses are:
Code:
VIA: EQU $6000 ; The base address of the 6522 Versatile Interface Adapter is $6000.
PB: EQU VIA ; Its port B is at that address.
PA: EQU VIA+1 ; Its port A is at address $6001.
DDRB: EQU VIA+2 ; Its data-direction register for port B is at $6002.
DDRA: EQU VIA+3 ; Its data-direction register for port A is at $6003.
T2CL: EQU VIA+8 ; Its timer-2 counter's low byte is at $6008.
T2CH: EQU VIA+9 ; Its timer-2 counter's high byte is at $6009.
SR: EQU VIA+10 ; The shift register is at $600A.
ACR: EQU VIA+11 ; The auxiliary control register is at $600B.
PCR: EQU VIA+12 ; The peripheral control register is at $600C.
IFR: EQU VIA+13 ; The interrupt flag register is at $600D.
IER: EQU VIA+14 ; The interrupt enable register is at $600E.
(The address $600F is the same as $6001 except that handshaking on the CA1 and CA2 lines was forced off even if you had it selected in the PCR at address $600C.) The computer's address decoding only has to select the VIA (or other IC) at the desired address. The selection of the individual registers
within the VIA is handled internally to the VIA itself. It has four address-line inputs to pick one of 16 addresses there once the chip-select inputs are true. The four address-line inputs are typically connected to A0 through A3 of the system's address bus.