A simple 6502 SBC. Request for comments

[mdpye]

Well, several late evenings and one bored-of-hearing-about-it girlfriend later...

Here is the schematic for "release candidate 1", and an SVG of what I might sent to the board house. Unfortunately SVG is the best output I can find from Kicad's PCD editor. edit: Scratch that, the forum doesn't allow SVG attachments. I've printed the SVG as a PDF. (cf. https://xkcd.com/763/)

I've incorporated the flip-flop on the clock, jumper headers for modifying the memory map, an NMI button (debounced the same way as the reset signal, because I can't get a nice double pole switch for the SR flip-flop debouncer) and possibly some other bits...

I have one final question about AC construction - On the large DIP packages, it's very difficult to get the decoupling cap close to both power pins, they're just too far apart, and signals need to be routed between. I've mostly gone for putting the cap near the ground pin and then bridging it directly to the internal Vcc plane. Would placing one cap on each of the Vcc and ground pins be better? Or should I really be going back and finding a way to put a single cap equidistant and directly between the package's power pins?

I've excited, and apprehensive... the PCB will cost slightly over $100 in full 4 layer. The extra space left around the EEPROM is so that a ZIF socket will fit...

[GARTHWILSON]

If you have both a power plane and a ground plane (and they're true planes, not copper pours which don't qualify as a plane), I don't think it would matter which of the two ways you do it. Myself, I would put the capacitor next to the power pin, with the shortest possible connection from the pin to the capacitor, and from the capacitor to the ground plane. Dr. Howard Johnson had a good article on that, but now you can't see it anymore without paying, so my link is basically dead. [Edit: I'm not sure which article I was thinking of when I wrote this, but I found his articles available, free, in the archives, at https://web.archive.org/web/20120302190 ... eyword.htm .]

[mdpye]

Thanks, I'll do that. By placing the caps on the underside of the board, I should be able to put them really close to the ground supply pins. I am going for a proper 4 layer board with true Vcc and ground planes on the internal layers. It's twice as expensive, but everything I've read here suggests I should just do it. It also simplifies routing a lot, and I'm a bit of a board layout novice, so that's a big plus.

[GARTHWILSON]

Assuming you'll be assembling by hand, you can also put vias in the pads themselves, further saving board space and facilitating routing and reducing inductance. You can't do that for production unless these vias are plugged and plated over, because when they screen the solder paste on, anywhere there's a hole, the solder paste will squish out the other side and make a big mess. An exception might be in that now we have a supplier that doesn't make a silkscreen for solder paste, but they actually spray it on kind of like an inkjet printer works, so the tool-up cost is reduced since it's all controlled in software only.

[BigDumbDinosaur]

mdpye wrote:

I have one final question about AC construction...

On my POC units, the bypass capacitor is placed as closely as possible to Vcc on the device being bypassed. The Vcc pin on the device is connected to the corresponding pin on the capacitor and the capacitor is what makes the connection to the internal power plane. This arrangement is based upon Dr. Howard Johnson's and others' recommendations and is one I have used for years. The other side of the capacitor is connected to the ground plane, as is the ground pin of the device.

The attached illustration of POC V2.1's four-layer PCB shows this layout arrangement—look at C8 and U8 (center) for an example.

POC V2.1 PCB

[mdpye]

Thanks. I notice you're using some pretty fat power traces in various places. I don't think they're going to be delivering loads of current, does a fatter trace help reduce noise on the power lines? I imagine the opposite would be true for a signal line, although that's an intuition, and my intuition about power is the opposite (like, the object is to stay stable, not switch quickly!)

[mdpye]

Quote:

Assuming you'll be assembling by hand, you can also put vias in the pads themselves, further saving board space and facilitating routing and reducing inductance.

Ah, that's good to hear. I had placed a lot of vias inside pads for the reasons you mentioned, but a quick Google convinced me to change them after reading about "solder slurping" problems. I was sceptical based on my experience hand soldering, but I can see how forced application of paste would be a problem. That didn't occur to me, but now I understand I'm more comfortable breaking with "accepted best practice"

I'll probably move some of them back to the pads where it neatens things or shortens power delivery lines

[Alarm Siren]

mdpye wrote:

Thanks. I notice you're using some pretty fat power traces in various places. I don't think they're going to be delivering loads of current, does a fatter trace help reduce noise on the power lines? I imagine the opposite would be true for a signal line, although that's an intuition, and my intuition about power is the opposite (like, the object is to stay stable, not switch quickly!)

Fatter traces = less resistance and impedance, neither of which are things you want on a power line.

[GARTHWILSON]

I wouldn't worry too much about that. A .008" trace of 1oz copper is good for a half amp of current at 20°C rise, and has less than a fifth of an ohm's resistance at three inches' length, meaning a half an amp on that teeny trace would drop about one-tenth of a volt across three inches. 5mA, or 1% of half an amp, would cause about 1mV of drop across three inches. The ratio of width to separation from the ground plane does affect characteristic impedance for fast AC signals; but when there's a bypass capacitor from the power trace to ground right at the IC anyway, neither of these things matter.

[Alarm Siren]

I agree that it is not of great importance in this case, but that is why one typically has fatter traces for power nets - or if you've got a lot of current. Even if its not necessary, if you have the room it can only help.

[Dr Jefyll]

Alarm Siren wrote:

I agree that it is not of great importance in this case, but that is why one typically has fatter traces for power nets - or if you've got a lot of current. Even if its not necessary, if you have the room it can only help.

Hmm. Not wishing to appear contrary, but this isn't always true, at least not with regard to the VCC trace. Let's assume the GND trace *is* nice and fat, or is an actual ground plane. Also assume that near each chip is a bypass cap attaching the chip's VCC pin to the fat trace or ground plane. This satisfies the need for a good AC connection between the various chips (Garth mentioned this, too). IOW, the VCC trace can be skinny because it only needs to carry a little bit of DC. There's no significant advantage if it's fat.

But a fat VCC trace can actually be a disadvantage in certain troubleshooting situations, such as when a chip or a bypass cap has shorted. You're better off to have skinny VCC traces because their resistance is high enough that there'll be a measurable voltage drop across the trace that feeds the shorted component. (Have been there and done this IRL -- a tidy solution to an otherwise nasty situation.)

[BigEd]

Hmm, that's an odd kind of advantage! Seeing Garth's calculation of a tenth of a volt drop, I think I'd rather have the fat trace...

[BigDumbDinosaur]

Dr Jefyll wrote:

But a fat VCC trace can actually be a disadvantage in certain troubleshooting situations, such as when a chip or a bypass cap has shorted.

Fortunately, I've not had anything like that occur in one of my contraptions—yet! I'm depending on the PC power supply I use to run my POC units to kick itself off-line if something does short. If it doesn't...well, I guess I'll have a little mess on my hands.

[GARTHWILSON]

BigEd wrote:

Hmm, that's an odd kind of advantage! Seeing Garth's calculation of a tenth of a volt drop, I think I'd rather have the fat trace...

The tenth of a volt drop was for 500mA through 3" of .008" on 1oz copper. For 5mA it's on 1mV. for 500µA (getting closer to what one CMOS IC might take), it's only 100µV. IOW, a .008" trace is plenty wide.

[Dr Jefyll]

BigEd wrote:

Hmm, that's an odd kind of advantage! Seeing Garth's calculation of a tenth of a volt drop, I think I'd rather have the fat trace...

You need to keep the numbers in perspective. Notice that a drop of one-tenth volt hardly puts a dent in the 5% tolerance of many digital IC's; moreover the half-amp figure Garth chose is far more than most IC's require.

FWIW, the troubleshooting case I cited involved heavy current and rather fat traces. But it's all a matter of proportion. The traces were not unnecessarily widened; if they had been then I'd have been sunk.