Well, several late evenings and one bored-of-hearing-about-it girlfriend later...
Here is the schematic for "release candidate 1", and an SVG of what I might sent to the board house. Unfortunately SVG is the best output I can find from Kicad's PCD editor. edit: Scratch that, the forum doesn't allow SVG attachments. I've printed the SVG as a PDF. (cf.
https://xkcd.com/763/)
I've incorporated the flip-flop on the clock, jumper headers for modifying the memory map, an NMI button (debounced the same way as the reset signal, because I can't get a nice double pole switch for the SR flip-flop debouncer) and possibly some other bits...
I have one final question about AC construction - On the large DIP packages, it's very difficult to get the decoupling cap close to both power pins, they're just too far apart, and signals need to be routed between. I've mostly gone for putting the cap near the ground pin and then bridging it directly to the internal Vcc plane. Would placing one cap on each of the Vcc and ground pins be better? Or should I really be going back and finding a way to put a single cap equidistant and directly between the package's power pins?
I've excited, and apprehensive... the PCB will cost slightly over $100 in full 4 layer. The extra space left around the EEPROM is so that a ZIF socket will fit...