TTL 6502 Here I come

[Drass]

BigDumbDinosaur wrote:

Use a small signal Schottky diode to isolate RDY from whatever is connected to it, along with a suitable pullup resistor in the 2.2K to 3.3K range.

Thanks for the tip BDD. I took the opportunity to google around and learn a bit about basic applications for diodes. Very helpful to get a pointer in the right direction.

And speaking of helpful, ttlworks was very kind to merge the 4 board files of the CPU into a beautiful panel (unfortunately not something I could do myself without the full version of Eagle CAD). Thank you ttlworks!

It's been a long time coming, but it's sure exciting to finally get here. And now it's off to the board house .. ahoy!

Attached are the op and bottom layers of the panel.

[dwight]

I don't know why you need the diode.
The RDY pin is a pull down only. Any tristate or
open collector device can be tied to it.
One can even use a NPN transistor.
Maybe I've misread the specification but I believe it is
clear.
" The RDY pin can still be wire ORed. "
Dwight

[BigDumbDinosaur]

dwight wrote:

I don't know why you need the diode.
The RDY pin is a pull down only. Any tristate or
open collector device can be tied to it.
One can even use a NPN transistor.
Maybe I've misread the specification but I believe it is
clear.
" The RDY pin can still be wire ORed. "
Dwight

The diode is necessary if the device driving RDY is not open collector. In most cases, wait-state logic will end up with the output of a flop controlling RDY.

[ttlworks]

BigDumbDinosaur wrote:

Use a small signal Schottky diode to isolate RDY from whatever is connected to it, along with a suitable pullup resistor in the 2.2K to 3.3K range.

Nice idea...
if the rise time of the RDY signal would be too slow, we would have to tinker with the resistor value...
or to put a 22pF capacitor in parallel to the diode.

LL101A Schottky diode looks nice: 40V \ 30mA \ 1ns
http://www.mouser.com/ds/2/427/ll101a-103152.pdf

[ttlworks]

Now the stats for the first prototype, correct me if I'm wrong:

;---

Register PCB: 56 ICs on top, 33 ICs at the bottom, 89 ICs in total.

ALU & CU PCB: 63 ICs on top, 49 ICs at the bottom, 112 ICs in total.

K24 PCB: 39 ICs on top, 0 ICs at the bottom, 39 ICs in total.

SBC PCB: 12 ICs on top, 15 ICs at the bottom, 27 ICs in total.
(W65C02 and oscillator ICs counted, resistor networks not counted).

;---

CPU without K24 has 201 ICs in total.

CPU with K24 has 240 ICs in total.

[ttlworks]

After looking around a little bit in the internet what the fastest TTL implementation of the 6502 might have been,
I stumbled over the TK20, a commercially sold product from 1987.

PDF with some description (German text) is here:
http://www.schaakcomputers.nl/hein_veld ... oKit-1.pdf

PALs and 74F, 100 ICs (including RAM), 18W, cost 1598 DM (18 MHz \ 1987), maximum speed 16..18 MHz (some TK20 made up to 20 MHz).
// 'Speed' here means the clock frequency at which the TK20 had stopped to work "reliable".

NMOS 6502 instruction set, 65C02 instruction set was "optional".

Since TK20 was intended to be used as an accelerator for chess computers,
it's an interesting question if TK20 had supported NMOS6502 decimal mode and NMOS6502 "illegal" OpCodes...
because supporting those things most certainly would affect speed and the amount of chips required.

TK20 already had been mentioned in the forum some years ago:
viewtopic.php?f=3&t=2010&sid=3f0475444a ... 3bccf72667

Had no luck in finding any more documentation\info\patents related to the TK20.

;---

Hmm... if OurCPU would make it to work in a reliable way at 21 MHz, this would break a 30 years old speed record.

[Drass]

It's here !!!

Man, oh man ... it's a beast:

Card A: Registers, Card B: ALU & CU, Card C: K24 and Card D: SBC - all in one panel. I had a quick look and noticed some vias were uncovered (I specified tented vias). That may prove to be a problem, since some of these vias are quite close to adjacent pads and I may bridge them when soldering. We'll have to see about that. The more immediate issue, however, is the v-scoring ...

The board house description is that a "V" shaped groove is "scored" into the panel on both the top and bottom surfaces along the boundary lines between each board (the groove is just visible in the pic above on the edge of the panel). The idea is that the individual boards can be snapped apart along these grooves. Sounds straight forward enough, but in fact the cuts in this instance are on the top-side only and enough material remains to make the panel flex unnervingly rather than snap. I'm thinking an exacto knife and a ruler may help cut a deep enough groove for a clean snap, but any suggestions on this 'score' are most welcome.

Anyway, I'm delighted to have the panel here. It will be a few days yet before I can get soldering - can't wait ...

Cheers for now,
Drass

[GARTHWILSON]

I'm not sure what you're saying the problem is; but our company has gotten loads of boards with the scoring, and the snap-apart feature has always worked perfectly. Never a problem. That said, there are times we get them routed instead, particularly when we need all usable the room we can get on the board, and the exact dimensions are more critical.

[Dr Jefyll]

Drass wrote:

It's here !!!

Wow! Congrats! (Now the fun really starts! )

Quote:

the cuts in this instance are on the top-side only and enough material remains to make the panel flex unnervingly rather than snap

"Flex unnervingly" sounds like a large-radius bend. For best chance of a clean break you want a small-radius bend. In other words confine and concentrate all the bending stress to the region within a millimeter or so of the score.

Maybe I'm stating the obvious, but the material NOT in the bend zone can be held flat (held un-bent) by use of an improvised clamping apparatus. For example, lay the PCB on a countertop (or the edge of a table saw, if you have one) then lay a piece of lumber on top, with downward pressure applied to create a sort of vise which clamps the PCB. The jaws of the "vise" should grip should fairly close (1-2 mm) to where the score is. Then use another piece of lumber to press down on and break off the unsupported half of the PCB. Again, to keep the bend radius small you wanna do your best to apply the downward pressure fairly close to where the score is.

(Probably the absolutely ideal tool for this job is a bending brake, as used for sheet-metal work. But even an improvised apparatus may be overkill, judging from Garth's remarks.)

-- Jeff

[ttlworks]

Congrats: the PCBs have arrived.

Jeff already made some good suggestions.

Another idea would be to take an "expandable" piece of FR4 PCB material,
then to visit a hardware store to see what tools or machines they have on stock for cutting glass or ceramic tiles.

Some of the hardware stores even rent tools or machines to customers...

[BigDumbDinosaur]

ttlworks wrote:

Congrats: the PCBs have arrived.

Jeff already made some good suggestions.

Another idea would be to take an "expandable" piece of FR4 PCB material,
then to visit a hardware store to see what tools or machines they have on stock for cutting glass or ceramic tiles.

Some of the hardware stores even rent tools or machines to customers...

I had to trim some PCBs a while back and used a small keyhole saw for the purpose. After cutting off the excess of the PCB I used a fine-cut file to clean it up.

[ttlworks]

Unfortunately, there isn't enough place between the individual PCB layouts in that panel for using something like a saw.

Hmm... the PCBs have 4 layers, and the two inner layers are GND and VCC supply layers.
After "breaking" the panel into four PCBs "somehow" and "deburring" the edges of the PCBs,
maybe it would be a good idea to check for a short circuit between the supply layers before soldering starts...

Sandpaper (which comes in different grit sizes) also could be used for "deburring" the edge of a PCB.
// The trick is to move the PCB, not the sandpaper.

Drass wrote:

I had a quick look and noticed some vias were uncovered (I specified tented vias). That may prove to be a problem, since some of these vias are quite close to adjacent pads and I may bridge them when soldering.

When covering/protecting the IC pads on the PCB with paper or cardboard, maybe you could try to paint those uncovered vias
which are too close to the IC pads with green nail polish or such.

Protecting the IC pads on the PCB with transparent tesa tape (tm) while painting probably would leave some glue on those IC pads...
...what won't simplify soldering the ICs later.

[GaBuZoMeu]

The term to separate pcb's is (pcb) depaneling. You may search for that. Tools are pretty expensive. Perhaps in your vicinity their is a company having such a tool. Then it's not a great deal for them to separate the pcb's unless you have already placed the components.

[GARTHWILSON]

ttlworks wrote:

Hmm... the PCBs have 4 layers, and the two inner layers are GND and VCC supply layers.
After "breaking" the panel into four PCBs "somehow" and "deburring" the edges of the PCBs,
maybe it would be a good idea to check for a short circuit between the supply layers before soldering starts...

Hopefully the planes were not brought out all the way to the edge, but stop .010" or so from the cut.

[Windfall]

Drass wrote:

It's here !!!

That is so pretty ! How fast will it be ?