Ambiguities with T1 timer

[Vladimir]

Studying the material foundations of the 6502 world, I came across an incomprehensible thing.
As far as I understand, hardware reset does set to zero all registers of R65C22.
As far as I understand, reading of upper half of T1 timer does not affect the state of the counter (at least I have not seen mention of this in the datasheet). But, the following program outputs into the port PA1 alternating values $00 and $FF, I would say, 'meander'.

Code: Select all

RESET	       LDA #$FF	        ;All pins of port A are outputs
	            STA DDRA1
LOOP	        LDA T1C_H	;reading upper half of T1 counter (reg#5)
	            STA ORA1	        ;output into port PA1
               BRA LOOP

What's the catch?

[GARTHWILSON]

What I'm looking at in my Synertek book says, "The reset input clears all internal registers to logic 0 (except T1 and T2 latches and counters and the Shift Register). [...]"

See also viewtopic.php?p=2311#p2311 in the "Tip of the Day" column

[Vladimir]

Thank you Garth, I read the tips. It seems that before the first loading the counter is in undefined undocumented condition. After the loading of it the further behavior of the timer becomes totally predictable (unstoppable count begins and all the features in accordance with datasheet). I experimented with 'one shot mode' only for the moment.

[Dr Jefyll]

Vladimir wrote:

the following program outputs into the port PA1 alternating values $00 and $FF

6522 counters count down and, in some modes, reload upon underflow. The $FF you mentioned could be the result of underflow in the high-byte, and the 00 could happen to be the uninitialized value reloaded into the high-byte.

As for bits initialized upon reset, manufacturers typically only do what's necessary. For example with the 6522 it's necessary to set the port pins to input mode upon reset, and manufacturers include circuitry for that. If the mode were left to chance then there'd be a risk of contention -- I mean if a pin tries to be an output but also happens to be connected to an output. (Hm, maybe I didn't explain that very well.. ) Anyway, in regard to 6522 timers no harm can result if the mode isn't initialized to a known state, so it's not surprising if the manufacturer didn't include circuitry to initialize the timer mode.

If the data sheet specifically mentions a bit being initialized upon reset, fine. Otherwise it's best to assume nothing. This applies generally, not just to 6522.

[Vladimir]

> 6522 counters count down and, in some modes, reload upon underflow. The $FF you mentioned could be the result of underflow in the high-byte, and the 00 could happen to be the uninitialized value reloaded into the high-byte.....

You're absolutely right, I checked.
Immediately after reset, the counter is already running, measuring out the shortest interval (two Ф2 clocks long). It looks like this:
$0000 - $FFFF - $0000 - $FFFF - $0000 and so on... Two clocks - this is even number. My reading cycle (see above) is 11 clocks: LDA+STA+BRA=(4+4+3). This is odd number. Therefore alternating values... Inserting in the cycle a dummy instruction to get an even number of clocks, I was doing a constant level of output instead of alternating values.

[Dr Jefyll]

Vladimir wrote:

This is odd number. Therefore alternating values... Inserting in the cycle a dummy instruction to get an even number of clocks, I was doing a constant level of output instead of alternating values.

Clever! Thanks for sharing your results.

Quote:

Immediately after reset, the counter is already running, measuring out the shortest interval

Okay, but just a reminder -- you can't rely on this behavior unless it's documented.

[Vladimir]

If something is documented, it also does not mean that it's true. A couple of examples.
My R65C22 datasheet says:
"A precaution to take in the use of PB7 as the timer output concerns the Data Direction Register contents for PB7. Both DDRB bit 7 and ACR bit 7 must be 1 for PB7 to function as the timer output. If one is 1 and other is 0, then PB7 functions as a normal output pin, controlled by ORB bit 7."
In fact, I have seen nothing of the kind. I did not touch DDRB, but timer pulses on line PB7 exist, therefore writing "1" into ACR bit 7 is enough. I remember, I have read another datasheet, for MOS6522, that says:
" PB7 will act as an output if DDRB7 = 1 or if ACR7 = 1. However, if both DDRB7 and ACR7 are logic 1, PB7 will be controlled from Timer 1 and 0RB7 will have no effect on the pin."
It is more like the truth.
Another interesting thing is a pull-up resistors. Contrary datasheet all PA, PB, CA, CB lines of my VIA (except the CA1) are pulled up to Vdd.
The date of manufacturing is 1423. Frequency capabilities are unknown (no designator, there was a topic about this, viewtopic.php?f=12&t=4199). Bought at Aliexpress.
Maybe, chinese counterparts?

[GARTHWILSON]

Quote:

Another interesting thing is a pull-up resistors. Contrary datasheet all PA, PB, CA, CB lines of my VIA (except the CA1) are pulled up to Vdd.
The date of manufacturing is 1423. Frequency capabilities are unknown (no designator, there was a topic about this, viewtopic.php?f=12&t=4199). Bought at Aliexpress.
Maybe, chinese counterparts?

I was bit by this years ago. Unlike WDC's, the Rockwell VIA, even though CMOS, has LSTTL inputs for the port pins. I thought they would be high-impedance so I could have weak pull-downs to make for a logic 0 when something wasn't actively pulling a pin up; but it didn't work, since an LSTTL input is normally high unless you pull it down pretty hard. These were real Rockwell VIAs that I got in the early 1990's.

[Vladimir]

The voltage at not connected input of my VIA is nearly Vdd. To halve it, I need pull-down resistor about 6k Ohm.
For some reason I thought that the voltage of free LSTTL input should be less than Vdd. Maybe 3.5V (at Vdd=5v) or something like that. Isn't it? And we need pull-up's to shift level from 3.5 to 5.0 volts. If an input keeps level at Vdd without pulling up, such one should not be in need of extra assistance, it needs no shifting. Is my understanding correct?

[Dr Jefyll]

Vladimir wrote:

For some reason I thought that the voltage of free LSTTL input should be less than Vdd. Maybe 3.5V (at Vdd=5v) or something like that. Isn't it?

You're right. Actual LSTTL inputs will float to roughly 3 or 3.5 volts when left unconnected.

Garth said, "the Rockwell VIA, even though CMOS, has LSTTL inputs for the port pins" and I'm sure he simply means Rockwell VIA ports inputs are made to behave similarly to LSTTL. The port inputs accept TTL voltage levels -- which AIUI is fairly easy for the manufacturer to arrange, even on a CMOS chip. Also, each input has an internal pullup attached, which is unusual for a CMOS chip but, again, not difficult to do.

The difference, as you say, is that the pullup pulls higher than an actual LSTTL input would. But I doubt anyone considers this a problem. In fact the higher voltage may be an advantage in some cases.

[GARTHWILSON]

I misspoke. My 1987 Rockwell data book specifically says for the R65C22, on pages 1-46 and 1-47, that although CA1 is a high-impedance input, all the other I/O lines represent two TTL loads in the input mode (not an LSTTL load)!! I missed it the first time around, and now it's even worse than I remembered.

[Vladimir]

GARTHWILSON wrote:

... now it's even worse than I remembered.

In fact all is much better against datasheet. Recall, the actual value measured by me is equivalent to one LSTTL input.