Finally starting the schematic for my first W65C02 SBC

[billylegota]

After deciding on what memory map to use (thanks to BDD, Ed, and Garth for all their valuable input), I have started work on the preliminary schematic for my first W65C02 SBC.

For those interested here are the features that I wanted in my build:

• 1. A simple board design that could be soldered by hand (no SMD).
  2. Enough IO to last me for a while, but not so much that it would make the memory decoding or board overly complex.
  3. The ability to interface with this great VT100 compatable board.
  4. The ability to select ROM banks and boot from different ROMs (I have a dip switch to do this).

Based on those criteria I decided to go with 2 VIAs (expandable to 4 via unpopulated sockets), 2 ACIAs, 16KiB of RAM (64KiB with upper 3/4 unused), and 32KiB of ROM (with bank switching via a dip switch).

My memory map (basically stolen from Garth's awesome 6502 Primer):

Code: Select all

%00xx xxxx xxxx xxxx - RAM
%0100 0000 0001 xxxx - VIA 1
%0100 0000 0010 xxxx - VIA 2
%0100 0000 0100 xxxx - VIA 3 (unpopulated)
%0100 0000 1000 xxxx - VIA 4 (unpopulated)
%0100 0001 0000 xxxx - ACIA 1
%0100 0010 0000 xxxx - ACIA 2
%1xxx xxxx xxxx xxxx - ROM

It should be noted that four additional VIAs or ACIAs could be added to the IO but have not been in order to keep board size and cost to a minimum.

The decode logic I will be using is as follows (also basically stolen from Garth's primer):

Which finally brings me to what little part of my schematic I have started on:

Any comments questions and such on any part of my design / design process would be much appreciated (I am mostly concerned about my schematic thus far).

I would also love it if someone would be able to answer any of the following questions for me:

• Does it make sense to put a bypass cap on the power input? If so what kind of cap and how large should it be?
  Should I replace my clock circuit with an all in one IC? If so are there any reccomendations for a specific one?
  Does it make sense to have 2 of my 4 VIA sockets be unpopulated (Should I populate them or just have 2 total)?

Thanks to everyone on the forum for being so friendly and supportive. I know that it must be slightly annoying having to explain everything to a 16 year old .

[barrym95838]

Bypass capacitors are supposed to help smooth out unwanted "static" from the high harmonics associated with digital switching. With that in mind, they should probably be placed as close as possible to the "noisiest" ICs, and should always be connected from +5V to Ground, not in series with your power supply switch, as you presently show in your schematic.

I am not qualified to comment on the rest of your schematic.

Mike B.

[GARTHWILSON]

Yes, bypass capacitors go as close as possible to the ICs' power & ground pins, with leads as short as possible. Monolithic ceramic ones work well.

SMT ICs with .050" lead spacing are pretty easy to solder with a little practice. You don't need a tiny tip on the iron either. DIPs are always easiest of course though.

Don't use 74LS. The reset circuit in particular won't work with it, because the series resistors cannot pull the inputs down anywhere near hard enough to qualify for a logic "0". Use CMOS, like 74HC or 74AC.

For the clock oscillator, just use one in a can. They plug into 14-pin or 8-pin DIP sockets, have everything onboard (so you'll save board space), and cost about the same as just the crystal by itself.

[billylegota]

Barrym,

Quote:

Bypass capacitors are supposed to help smooth out unwanted "static" from the high harmonics associated with digital switching. With that in mind, they should probably be placed as close as possible to the "noisiest" ICs, and should always be connected from +5V to Ground, not in series with your power supply switch, as you presently show in your schematic.

I don't quite know why I placed a capacitor on the +5V input which concerns me... maybe I am too tired to be doing this.

Garth,

Quote:

Don't use 74LS. The reset circuit in particular won't work with it, because the series resistors cannot pull the inputs down anywhere near hard enough to qualify for a logic "0". Use CMOS, like 74HC or 74AC.

I don't plan on doing so, I was trying out ExpressPCB and only 74LS was available in the part library. I have since switched to DipTrace and am using the 74HC04 and 74HC14.

Quote:

For the clock oscillator, just use one in a can. They plug into 14-pin or 8-pin DIP sockets, have everything onboard (so you'll save board space), and cost about the same as just the crystal by itself.

Is there any particular manufacturer that is good or will just any old 1MHz - 4MHz oscillator work?

On a side note, I may end up only having 2 VIAs (without any unpopulated sockets) in order to reduce board size and due to DipTrace's 300 pin limit (although I think I can upgrade to the free education version which has a max of 500 if I register through my school).

[GARTHWILSON]

billylegota wrote:

Quote:

Don't use 74LS. The reset circuit in particular won't work with it, because the series resistors cannot pull the inputs down anywhere near hard enough to qualify for a logic "0". Use CMOS, like 74HC or 74AC.

I don't plan on doing so, I was trying out ExpressPCB and only 74LS was available in the part library. I have since switched to DipTrace and am using the 74HC04 and 74HC14.

Good. The pinout is the same, and it won't matter what the CAD thinks as long as you're putting the right physical parts in.

Quote:

Quote:

For the clock oscillator, just use one in a can. They plug into 14-pin or 8-pin DIP sockets, have everything onboard (so you'll save board space), and cost about the same as just the crystal by itself.

Is there any particular manufacturer that is good or will just any old 1MHz - 4MHz oscillator work?

I have not shopped for them recently (I probably have hundreds in stock), but the differences are probably in the amount of power supply current, the accuracy, and make sure you get the right voltage for your project. It should be able to pull up to nearly 5V too, so it probably needs to be CMOS.

[billylegota]

HCMOS should be fine correct? The only DIP 1 MHz CMOS oscillators I could find on Mouser are out of stock and require a minimum order of 10000 (I don't need that many yet ).

The HCMOS one I was looking at is here.

[BigDumbDinosaur]

billylegota wrote:

HCMOS should be fine correct? The only DIP 1 MHz CMOS oscillators I could find on Mouser are out of stock and require a minimum order of 10000 (I don't need that many yet ).

The HCMOS one I was looking at is here.

That one should work fine.

A note concerning clock oscillators for future reference. You need not concern yourself right now with this information, but may eventually find it useful.

In theory, a clock oscillator's output has an exact 50 percent duty cycle. In practice, most oscillators will be anywhere from 45 percent to 55 percent. At low Ø2 clock rates such output asymmetry can usually be safely ignored. As you push the Ø2 clock rate ever closer to the maximum rating of the clocked device, output asymmetry has the potential to violate device timing and may lead to mystery problems. Jeff Laughton (Dr. Jefyll) has a lucid discussion on timing at his website, which among other things, shows what can happen when clock asymmetry inadvertently bumps against device specs.

When I designed my POC unit I decided to run the clock oscillator's output through a flip-flop to eliminate asymmetry as a possible problem causer. Here's the circuit I used:

Ø2 Clock Generator

Due to the way in which flops work, the outputs at PHI1 and PHI2 have an exact symmetry, and are also exactly 180 degrees out of phase with each other. Also, the flop's output transition time is extremely short, producing a very sharp signal, and drive is strong. The frequency at PHI1 and PHI2 will be one half that of the oscillator.

As I said, this is not important right now, but will become so when you finally get to where you want to run the 65C02 at full speed (officially 14 MHz).

[BigEd]

billylegota wrote:

Does it make sense to put a bypass cap on the power input? If so what kind of cap and how large should it be?

It's normal to have two kinds and sizes of capacitor: small ones close to each power-hungry chip, and a larger one close to the power supply point. Looks like the smaller ones are called bypass and the larger one is called bulk. 10uF electrolytic for the big one, 0.1uF for the small ones, maybe. Make sure the electrolytic one is the right way around. If you have inadequate capacitance, you could get unreliability, which is really hard to debug. If you don't get unreliability, you might mistakenly conclude that capacitance is unnecessary - in fact you'd be better off concluding that you were lucky this time.

[Michael]

Hi Billy. Welcome to the community.

A small microcontroller might also be used for a clock source with a relatively small foot print on your PCB. The crystal is actually optional if you can live with the ±1% frequency tolerance of the internal oscillator. In this case the extra pins could be used for a pair of jumpers to set the CPU Clock to 1, 2, 4, or 8-MHz during power-up or reset.

Have fun and good luck on your project.

Cheerful regards, Mike

[billylegota]

BDD,

Quote:

A note concerning clock oscillators for future reference. You need not concern yourself right now with this information, but may eventually find it useful.

In theory, a clock oscillator's output has an exact 50 percent duty cycle. In practice, most oscillators will be anywhere from 45 percent to 55 percent. At low Ø2 clock rates such output asymmetry can usually be safely ignored. As you push the Ø2 clock rate ever closer to the maximum rating of the clocked device, output asymmetry has the potential to violate device timing and may lead to mystery problems. Jeff Laughton (Dr. Jeffyl) has a lucid discussion on timing at his website, which among other things, shows what can happen when clock asymmetry inadvertently bumps against device specs.

When I designed my POC unit I decided to run the clock oscillator's output through a flip-flop to eliminate asymmetry as a possible problem causer. Here's the circuit I used:

I might add the flip-flop anyway so that if I want to change the clock speed later I can just swap out the oscillator without having any concern over asymmetry at higher speeds.

Quote:

It's normal to have two kinds and sizes of capacitor: small ones close to each power-hungry chip, and a larger one close to the power supply point. Looks like the smaller ones are called bypass and the larger one is called bulk. 10uF electrolytic for the big one, 0.1uF for the small ones, maybe. Make sure the electrolytic one is the right way around. If you have inadequate capacitance, you could get unreliability, which is really hard to debug. If you don't get unreliability, you might mistakenly conclude that capacitance is unnecessary - in fact you'd be better off concluding that you were lucky this time.

I'll put a ceramic cap bypassing every IC and an electrolytic cap at the power supply header just to be safe.

Mike,

Quote:

Hi Billy. Welcome to the community.

A small microcontroller might also be used for a clock source with a relatively small foot print on your PCB. The crystal is actually optional if you can live with the ±1% frequency tolerance of the internal oscillator. In this case the extra pins could be used for a pair of jumpers to set the CPU Clock to 1, 2, 4, or 8-MHz during power-up or reset.

Have fun and good luck on your project.

Thanks for the warm welcome.

I like the additional control that an MCU would add to the system but I don't think that a microcontroller would fit with the feeling that I am going for. When I build a second system I may use some less purist component choices (such as GALs / FPGAs and MCUs). I will keep this idea in mind though (seeing as I can get most PICs or AVRs for less than an all in one oscillator).

[BigDumbDinosaur]

BigEd wrote:

billylegota wrote:

Does it make sense to put a bypass cap on the power input? If so what kind of cap and how large should it be?

It's normal to have two kinds and sizes of capacitor: small ones close to each power-hungry chip, and a larger one close to the power supply point. Looks like the smaller ones are called bypass and the larger one is called bulk. 10uF electrolytic for the big one, 0.1uF for the small ones, maybe. Make sure the electrolytic one is the right way around. If you have inadequate capacitance, you could get unreliability, which is really hard to debug. If you don't get unreliability, you might mistakenly conclude that capacitance is unnecessary - in fact you'd be better off concluding that you were lucky this time.

Furthermore, I place a 0.1µF MLCC as physically close as possible to the input bulk electrolytic (I generally use 100µF there, as I've got a bunch of them). Electrolytics often have poor high frequency performance and hence may not do an adequate job of bypassing high frequency noise to ground. The MLCC handles that for the electrolytic. The below image shows how I did this on POC V1.1:

POC V1.1 Power Input

The bulk electrolytic is C21 and the MLCC is C20. My concern was that switching noise not get out on the power supply connections, hence the tight positioning of C20 with respect to the power input connector.

Each chip on the board has an MLCC bypass, as seen in the below image.

POC V1.1, Showing Bypass Caps

Here again, the MLCCs are placed as physically close as possible to the end of the device at which the VCC connection is present—you want the connection between the MLCC and the VCC pin to be as short as possible. Note that the clock oscillators are also bypassed—they can be a fertile source of noise.

It's best to think of bypass capacitors as like money: more is good!

[billylegota]

BigDumbDinosaur wrote:

Furthermore, I place a 0.1µF MLCC as physically close as possible to the input bulk electrolytic (I generally use 100µF there, as I've got a bunch of them). Electrolytics often have poor high frequency performance and hence may not do an adequate job of bypassing high frequency noise to ground. The MLCC handles that for the electrolytic. The below image shows how I did this on POC V1.1:

The bulk electrolytic is C21 and the MLCC is C20. My concern was that switching noise not get out on the power supply connections, hence the tight positioning of C20 with respect to the power input connector.

Each chip on the board has an MLCC bypass, as seen in the below image.

Here again, the MLCCs are placed as physically close as possible to the end of the device at which the VCC connection is present—you want the connection between the MLCC and the VCC pin to be as short as possible. Note that the clock oscillators are also bypassed—they can be a fertile source of noise.

It's best to think of bypass capacitors as like money: more is good!

I am going to add the electrolytic and MLCC to my power supply schematic. Is the following schematic correct?

[GARTHWILSON]

Yes, that's good. Make the monolithic ceramic capacitor's leads as short as you can, since they have inductance.

[billylegota]

I have finally settled on DipTrace as my schematic editor and have reworked the power supply, clock generator, and reset generator.

New power supply (now with bulk and bypass caps):

New reset generator (no massive change other than the bypass cap on the 74HC14):

New clock generator (changed to 4MHz with flip flop down to 2MHz):

The next part will take me a while as I need to make schematics for almost all the other parts in my build.

[BigDumbDinosaur]

billylegota wrote:

I have finally settled on DipTrace as my schematic editor and have reworked the power supply, clock generator, and reset generator.

A couple of notes.

1. The Maxim DS-1813 reset generator is a one-part solution to controlling /RESET. It is in a TO-92 package, so it has a real small footprint, and it requires no other parts other than a reset circuit pullup resistor to be functional. The DS-1813 automagically cycles /RESET low and then high when power is applied, plus repeats the cycle if something (e.g., a push button) pulls /RESET low.

   reset_controller_ds1813.pdf

   Maxim DS-1813 Reset Generator

   (206.15 KiB) Downloaded 168 times

2. Both /CLR and /PRE (aka /SET) on a 74x74 flip-flop must be pulled high in order for Q and /Q to follow changes at CLK and D.
3. The flop should be a 74AC74 or 74ABT74, not the 74HC74. The 74HC74's output transition time may not meet the 5ns maximum input transition time spec of the W65C02S (the tF and tR specs—refer to pages 25 and 26 in the data sheet). Despite the name ("HC" meaning "high speed CMOS"), 74HC devices are usually no faster than equivalent 74LS devices.