So I was reading about different architectures and DMA / cycle stealing came up a few times.

What I'm referring to is how a device, like a video controller, would access RAM during low phase (IIRC) of the CPU cycle. Allowing the video controller and CPU to use the RAM at effectively the same time.

I then started wondering how fast you could do that? If a '02 or '816 could run at 14 MHz, then I suppose a video controller could run at a maximum of 7 MHz. Correct?

Take VGA's frequency of 25 MHz (rounded down). You could clock the CPU at half that and get 12.5 MHz....nearly the limit. But then, you'd be limited to 6.25 MHz for the video DMA. Which means you'd only get 1/4 of the 640 pixels (160).

Anyway, I find it entertaining to think about these theoretical limits.

What are your thoughts on the maximum speed and if something like VGA is practical?

Thanks!

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Cat; the other white meat.

The Apple II did that, letting video access memory during phase 1 while the processor accessed it during phase 2, meaning two million accesses per second at 1MHz. Obviously timing gets more critical, and doing it at 12.5MHz+ on an '816 becomes an even bigger challenge (although you do get 12.5M DMA accesses per second, not just 6.25M).

For some applications, I like the idea presented in the topic "The secret, hidden, transparent 6502 DMA channel" at viewtopic.php?f=1&t=1160 .

Cycle-stealing is different.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Ah, yeah...you're right. I got my terminology mixed up.

I also liked the way Apple II did it. Really clever.

OK, my assumption was wrong then....which happens sometimes.

Using the following diagram, I believe you're right again. It would be 12.5 MHz for the VGA. Which would be 320 "fat" pixels for the normal 640 (not counting front/back porch).

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Cat; the other white meat.

It has been a long time now, but I apparently ran my SBC-3 at 14.318MHz and it used the low side of PHI2 to feed the composite display video data and the high side for the 65816.

See here -> viewtopic.php?p=9022#p9022

So yes, it is possible to do a VGA signal at a reduced horizontal pixel count.

Daryl

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Please visit my website -> https://sbc.rictor.org/

Thanks for the reply.

YES! Your SBC-3 has been a real inspiration to me. It's very close to my "Ideal 80's Computer". I'm actually tinkering with some FPGA as well. I was surprised at how quickly I got a stable VGA signal going with it. I'd really like to take a similar route as you. Using programmable logic to tie things together and provide video.

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Cat; the other white meat.

If you want to double your available video bandwidth, double up on the data bus width for the video memory, and use appropriate multiplexers / chip selects to interface the video memory to the CPU.

Do you have an example of this?

However, 320x200 pixels for VGA and '816 CPU seems pretty good to me.

Especially since early IBM's running around the same frequency only had CGA or EGA at best. It wasn't until 10 MHz seemed "slow" that VGA took off. Like perhaps 33MHz IIRC.

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Cat; the other white meat.

If you have fast enough memory and glue logic, how about doing two (or even more) video memory accesses during phase 1? Start with a clock that's some multiple of the processor's operating speed.

It seems like CGA was 320x200. I remember someone about 1990 who got an inexpensive PC with CGA but quickly upgraded after trying to lay out a PC board on it.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

That's certainly a good idea. I didn't think about that!

In fact, I've had an 8ns SRAM chip in my Mouser shopping cart for the last week or so. Maybe need to buy it...

But it's SMD so going to be a little annoying to prototype with it.

8ns SRAM with FPGA could probably do several calls during PHI1.

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Cat; the other white meat.

My 4-megabyte 10ns 5V SRAM module is made to be hobbyist-friendly.
http://wilsonminesco.com/WM-1_4Mx8SRAMm ... -12-15.pdf

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

See the Oric for an example of three accesses per cycle in a 6502 system:

CGA was 640 × 200 as implemented in the IBM PC. The Commodore 128's 80 column output was CGA-compatible, plus could do 640 × 400 in interlaced mode by tweaking some settings in the 8563/8568 video display controller.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

With only one color and black. Else the resolutions were much lower. And there was a maximum of 16 simultanous colors. What cbmeek will get is 320x200 and 256 colors, this will outperform CGA.

Ok, I just looked it up, like I should have done earlier. Wikipedia says:

CGA supports:


• 320×200 in 4 colors from a 16-color hardware palette. Pixel aspect ratio of 1:1.2.
  
• 640×200 in 2 colors. Pixel aspect ratio of 1:2.4

(The pixel ratio stems from rendering said amount of pixels on a 4:3 screen, a monitor ratio typical of that time.)

Text modes:


• 40×25 with 8×8 pixel font (effective resolution of 320×200)
  
• 80×25 with 8×8 pixel font (effective resolution of 640×200)

Extended graphics modes:


• 160×100 16-color mode
  
• Artifact colors using a NTSC monitor (16 colors from more than 100 possible)

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

With the right trickery CGA can do much, much better than that.. ask the guys behind 8088 MPH. 256 colours? No problem. Not enough? Okay then..