SBC-3 Speed Increase
SBC-3 Speed Increase
I have successfully doubled the 65816 speed on the SBC-3.
I have re-worked some of the timing within the XC95108 to remove the need for a 2x clock for PHI2. I have successfully run my SBC-3 at the full 14.318 MHz that the NTSC system is clocked at. While I have not tested it yet, the 16 MHz PAL version is likely to work as well.
I had to remove the Memory Protect feature, and still have more testing to perform. All other functions remain the same. I did have to increase the SPI Clock divisor. The final value has yet to be determined.
I'll post the final results once they have been verified.
For those interested, the XC95108 and the 28256 will need to be reprogrammed for this upgrade. All other parts remain unchanged. This is a firmware-only update.
Daryl
I have re-worked some of the timing within the XC95108 to remove the need for a 2x clock for PHI2. I have successfully run my SBC-3 at the full 14.318 MHz that the NTSC system is clocked at. While I have not tested it yet, the 16 MHz PAL version is likely to work as well.
I had to remove the Memory Protect feature, and still have more testing to perform. All other functions remain the same. I did have to increase the SPI Clock divisor. The final value has yet to be determined.
I'll post the final results once they have been verified.
For those interested, the XC95108 and the 28256 will need to be reprogrammed for this upgrade. All other parts remain unchanged. This is a firmware-only update.
Daryl
The NTSC version testing is complete. The 65816 on the SBC-3 board is stable at 14.318 MHz. The 65SPI divisor changes to 3 (originally 1).
I performed several serial downloads and DiskOS file transfers to comfirm the 65SPI worked properly.
I did not do a complete test of the 65C22's. However, since the ATMega8 uses CB1 of VIA1 for handshaking, basic communication is working and implies the remainder is working as well. I will eventually test some devices on these VIA's.
Next, bad news for PAL users. My initial tests failed. It appears that the 16MHz clock is too fast for the CPU in this layout. I get a stable picture from the XC95108, but the contents are random patterns. It is evident the 65816 did not execute the /reset code. Time permitting, I'll do further tests.
Please contact me via PM or email if you are interested in this upgrade.
Daryl
I performed several serial downloads and DiskOS file transfers to comfirm the 65SPI worked properly.
I did not do a complete test of the 65C22's. However, since the ATMega8 uses CB1 of VIA1 for handshaking, basic communication is working and implies the remainder is working as well. I will eventually test some devices on these VIA's.
Next, bad news for PAL users. My initial tests failed. It appears that the 16MHz clock is too fast for the CPU in this layout. I get a stable picture from the XC95108, but the contents are random patterns. It is evident the 65816 did not execute the /reset code. Time permitting, I'll do further tests.
Please contact me via PM or email if you are interested in this upgrade.
Daryl
Last edited by 8BIT on Tue Nov 03, 2009 2:01 pm, edited 1 time in total.
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Next, bad news for PAL users. My initial tests failed. It appears that the 16MHz clock is too fast for the CPU in this layout. I get a stable picture from the XC95108, but the contents are random paterns. it is evident the 65816 did not execute the /reset code. Time permitting, I'll do further tests.
Yes, that occurred to me as well. The EEPROM is only read while the 65816 is in reset, so I know that part is ok. The CPLD will run up to 20MHz on my Core, which has only a few parts and a small footprint. The most likely issue is the addition of the two VIA's and the 65SPI to the 65816 data bus and lower address bus, along with the increase in trace lengths.
When I have time to experiment more, I will remove the VIA's and 65SPI and test again.
thanks for the input!
Daryl
When I have time to experiment more, I will remove the VIA's and 65SPI and test again.
thanks for the input!
Daryl
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20 MHz & Beyond
8BIT wrote:
The CPLD will run up to 20MHz on my Core, which has only a few parts and a small footprint. The most likely issue is the addition of the two VIA's and the 65SPI to the 65816 data bus and lower address bus, along with the increase in trace lengths.
Another consideration is that your PCB layout appears to be constraining the maximum clock rate. Since it is a two-layer design, you have to consume real estate with the Vcc and GND traces, limiting how tightly you can pack your parts and how short and direct your signal traces can be. Also, Vcc and GND themselves add reactance issues, especially the dreaded ground bounce effect, which CPLDs generally do not well-tolerate.
Perhaps it's time to look at doing this unit on a four-layer board. You wouldn't have to place Vcc and GND everywhere and the inner power and ground layers would add some noise and crosstalk immunity—the latter could also be sabatoging timing. Only downside, of course, will be PCB cost...
Incidentally, extrapolation of WDC's Fmax vs VDD curve on page 27 of the current (Aug 3, 2009) data sheet suggests the MPU could run significantly faster than 20 MHz, although the MUXing of A16-A23, already a design issue at lower speeds, would become a major obstacle to running beyond 20 MHz. You'd probably be wait-stating the dickens out of everything.
x86? We ain't got no x86. We don't NEED no stinking x86!
Yes, I agree with your thoughts. A 4-layer board with PLCC or TQFP parts and tighter parts placement would be better.
However, I do not plan to expand the SBC-3 further. I am very content with the 7.159MHz (8 MHz PAL) performance. The fact that I got my board to run at 14.318Mhz is great, but I feel its operating pretty close to its limits, and will not attempt any further modification/enhancements.
I am working on the code for a RTL8019AS Ethernet interface. I have one on an old ISA board that connects to a VIA. The other is on an old EDTP.com ATA/Ethernet board based around the ATMega128. It would use the ATMega128 to handle the TCP/IP stack and communicate through the 65SPI.
After that, I will stop further development.
For those who might be thinking about Ethernet, I would also recommend researching the Microchip ENC28J60 Ethernet chip. It has an SPI/I2C interface and has a lot of following in the embedded arena's.
My other hobby is flying, and I have recently started down a path that includes building an airplane. I just don't have time for both and while I enjoy the 6502/65816/AVR's, I feel its time to explore my other interests.
Daryl
However, I do not plan to expand the SBC-3 further. I am very content with the 7.159MHz (8 MHz PAL) performance. The fact that I got my board to run at 14.318Mhz is great, but I feel its operating pretty close to its limits, and will not attempt any further modification/enhancements.
I am working on the code for a RTL8019AS Ethernet interface. I have one on an old ISA board that connects to a VIA. The other is on an old EDTP.com ATA/Ethernet board based around the ATMega128. It would use the ATMega128 to handle the TCP/IP stack and communicate through the 65SPI.
After that, I will stop further development.
For those who might be thinking about Ethernet, I would also recommend researching the Microchip ENC28J60 Ethernet chip. It has an SPI/I2C interface and has a lot of following in the embedded arena's.
My other hobby is flying, and I have recently started down a path that includes building an airplane. I just don't have time for both and while I enjoy the 6502/65816/AVR's, I feel its time to explore my other interests.
Daryl
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8BIT wrote:
My other hobby is flying, and I have recently started down a path that includes building an airplane. I just don't have time for both and while I enjoy the 6502/65816/AVR's, I feel its time to explore my other interests.
My current other hobby is large scale model railroading and I am scratch-building a 1.6 inch scale EMD F7 locomotive. I have a running chassis and am now working on the body. I don't have a particular time-frame for completion, except I hope to finish while I am still healthy enough to enjoy it.
x86? We ain't got no x86. We don't NEED no stinking x86!
OK, it's woefully off-topic, and probably lacks the appeal of replicating historical engines, but you folks might appreciate this home-made backyard monorail installation:
http://www.monorails.org/tmspages/Niles.html
http://www.monorails.org/tmspages/Niles.html
- BigDumbDinosaur
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Now, that is cool! Too bad my back yard is too small for anything like that (plus association rules would prohibit it). 
x86? We ain't got no x86. We don't NEED no stinking x86!
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Nightmaretony
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ElEctric_EyE wrote:
8BIT wrote:
..., I feel its time to explore my other interests.
Daryl
Daryl
"My biggest dream in life? Building black plywood Habitrails"
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It would use the ATMega128 to handle the TCP/IP stack and communicate through the 65SPI.
After that, I will stop further development.
After that, I will stop further development.
- the ATMega128 for ethernet & TCP/IP
- a VGA interface with instructions for placing text, scrolling, drawing lines, feeding ready-made graphics, etc.. I'd buy a video interface from you even if it were only for monochrome composite video with 480 dots across.
- IDE adapter
- PC keyboard to SPI with plenty of buffering so you can type ahead when the processor is too busy to pay attention to the keyboard
- other hardware interfacing, like A/D and D/A converters, UARTs, infrared, additional I/O lines, etc.
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Isn't it legal to sell a kit that isn't FCC approved if you advertise it as such? Something like, "This product has not received FCC type approval."?