Newbie-ish ROM and RAM decoding question

[dracosilv]

Okay.. on this page here: http://wilsonminesco.com/6502primer/addr_decoding.html

It shows decoding of RAM and ROM using NAND gates and inverters. I can see how to 'wire up' my lowest 32k of Static Ram, and.. I assume that if I wanted to wire up say, the next 16k of ram (8000h to BFFFh) I'd just use another few gates and inverters so that at the input of another NAND gate, the Phase 2 Clock would be '1' at the same time the Bank-Selection circuitry for A15 and A14 were properly 'active'? e.g when A15=1 and A14=0?

Sorry if this sounds like a 'stupid' question.. but for some reason i'm having a bit of a hard time wrapping my mind around the whole thing what with the Phase 2 clock needing to be high at the same time certain address lines are selected.. maybe my mind is just rusty with boolean logic after so many years of not making tables like this?

[Arlet]

Quote:

Sorry if this sounds like a 'stupid' question.. but for some reason i'm having a bit of a hard time wrapping my mind around the whole thing what with the Phase 2 clock needing to be high at the same time certain address lines are selected.

The purpose of adding the Phase 2 clock (PHI2) is to prevent a situation where the CPU can write to the wrong address. This could happen at the point that the RWB signal changes from 1 to 0 (starting a write), while the RAM is still selected from the previous cycle. Because the RWB signal, as well as the address lines, only change when PHI2=0, you can fix the problem by only writing to RAM when PHI2=1. This can be done by adding the PHI2 to the chip select logic (like in Garth's schematic), or adding the PHI2 to the write enable logic.

Garth's schematic is good if you want a minimal system with minimal parts, but if you want a bit more advanced address decoding, I would recommend removing the PHI2 qualification from your address decoding, and instead add it to the Write Enable logic to your SRAM. That way, it is kept separate from the address decoding, and makes both simpler to understand. There are several older threads dealing with this subject. for example viewtopic.php?f=4&t=2449

[BigDumbDinosaur]

dracosilv wrote:

Okay.. on this page here: http://wilsonminesco.com/6502primer/add ... html...I'd just use another few gates and inverters so that at the input of another NAND gate, the Phase 2 Clock would be '1' at the same time the Bank-Selection circuitry for A15 and A14 were properly 'active'? e.g when A15=1 and A14=0?...I'm having a bit of a hard time wrapping my mind around the whole thing what with the Phase 2 clock needing to be high at the same time certain address lines are selected.

Another means of decoding RAM and ROM is with a 74AC138 or 74AC139 or similar decoder. I attached the data sheets for your reading pleasure.

74ac138_decoder.pdf

74AC138 Decoder

(668.04 KiB) Downloaded 92 times

74ac139_decoder.pdf

74AC139 Decoder

(614.85 KiB) Downloaded 80 times

Be sure to heed Arlet's advice about not using the Ø2 clock as part of the decoding logic, essential with 65xx devices, such as the 65C22 and 65C51, which must be selected before the rise of the clock. Also, as Arlet advised, use Ø2 to qualify read/write accesses. This is especially important on writes, as the data bus may contain random content during Ø2 low. See below.

Non-65xx Device Read/Write Qualification Example

Note that Ø2 qualification of read/write accesses applies only to non-65xx devices. 65xx devices should have their RWB inputs directly connected to the microprocessor's RWB output.

[GARTHWILSON]

Quote:

as the data bus may contain random content during Ø2 low

and, more importantly, the address is not guaranteed to be valid and stable before the R/W\ line goes down, so you could write to unintended RAM addresses, corrupting things. We have had a couple of members get bit by this in past years. The data will be correct enough time before the end of the cycle though.

[dracosilv]

A bit of clarification, It wasn't the FACT of the clock being high/low to signify the read/writes.. it was more the juggling of the r/w AND the clock being in a certain state AND the address logic, creating, well.. a logiclal nightmare in my slightly sleepy-ish brain.

[randallmeyer2000]

Good question. It seems I've neglected such considerations as well. Thanks for asking the question, it saves me the bother, and I get to look over my design in light of this new/old information.

[randallmeyer2000]

I am especially uncertain about the 65C22. I guess it might have helped if I coded "in the old days"; or for that matter, now. I suppose I should put together a plan for my PCB clock circuit (and gather the parts too!).

With regard to I/O, I think Garth's plan ( http://wilsonminesco.com/6502primer/pot ... ml#BAS_CPU ) seems wisest to me. Generic pin headers. That way, any ol' connector might be interfaced. I might also make certain there's some kind of I2C bus, too. I think I saw some nifty I2C connectors on a thread here, somewhere. As a minimal system, that should suit my needs.

I don't think the Phi2 thing mentioned affects me? I think I just used 74HC138s and a 74HC311?( 3-input AND); I don't think that will cascade too much and mess with clock or synchronization. bUt I just read the sentence "You must have a way of making sure microprocessor cannot write to RAM while Phi2 is low" and now I must read that section again!

I still have to put some R/W lines and OE and CE and other things on my PCB plan. Being new to this, I definitely need to look at all the timing diagrams (I am no stranger to music, symphonies, orchestration and such! Should be easy!).

I have become sidetracked, today, by physics. Still curious about light computers and Moore's Law. Seems not all speeds of light are equal (hahaha! I knew that; index of refraction is ratio of speeds of light). I know you 6502-ers like new projects. Any 6502 optical-instantiations out there? (just 3,500 transistors, right? https://commons.wikimedia.org/wiki/File ... S_6502.jpg ). Maybe I'll leaf through my Edmund Optics catalog and try to build one for less than $1000 (optics are EXPENSIVE!). I guess I am OT (off topic), but the subject of delay is on my mind.

(In the following table, c refers to the speed of light in a vacuum,
or 300,000 kilometers per second.

Medium Propagation Speed
------ -----------------
Thick Coax .77c (231,000 km/sec)
Thin Coax .65c (195,000 km/sec)
Twisted Pair .59c (177,000 km/sec)
Fiber .66c (198,000 km/sec)
AUI Cable .65c (195,000 km/sec) )

http://stason.org/TULARC/networking/lan ... ltIAL-YG5I


And:


https://en.wikipedia.org/wiki/Velocity_factor

"

VF% Transmission line
95-99 Open-wire "Ladder" Line
80 Belden 9085 twin-lead
82 RG-8X Belden 9258 coaxial cable (foamed polyethylene dielectric)
66 RG-213 CXP213 coaxial cable (solid polyethylene dielectric) "

And:

https://en.wikipedia.org/wiki/Fiber-opt ... ord_speeds

"

In 2013, New Scientist reported that a team at the University of Southampton had achieved a throughput of 73.7 Tbit per second,

with the signal traveling at 99.7% the speed of light through a hollow-core photonic crystal fiber.[14] "

[GARTHWILSON]

randallmeyer2000 wrote:

( http://wilsonminesco.com/6502primer/pot ... ml#BAS_CPU ) seems wisest to me. Generic pin headers. That way, any ol' connector might be interfaced.

Note also that the pinout is such that if you plug the IDC on backwards, you won't damage anything.

Quote:

I might also make certain there's some kind of I2C bus, too. I think I saw some nifty I2C connectors on a thread here, somewhere.

I2C-6 proposed standard: viewtopic.php?f=4&t=2155 (and I just fixed the broken picture link.) It's hobbyist-friendly.

[BigDumbDinosaur]

GARTHWILSON wrote:

Quote:

as the data bus may contain random content during Ø2 low

and, more importantly, the address is not guaranteed to be valid and stable before the R/W\ line goes down, so you could write to unintended RAM addresses, corrupting things. We have had a couple of members get bit by this in past years. The data will be correct enough time before the end of the cycle though.

This is one of those chicken-or-egg things, depending on how one reads the timing diagram. Either way, read/write should always be qualified by Ø2 to eliminate any danger of corruption.

[BigDumbDinosaur]

randallmeyer2000 wrote:

I don't think the Phi2 thing mentioned affects me? I think I just used 74HC138s and a 74HC311?( 3-input AND); I don't think that will cascade too much and mess with clock or synchronization.

If you are worried about total prop time use 74AC logic instead of 74HC. In many cases, 74AC is at least twice as fast as 74HC, and also has better fanout.

Quote:

bUt I just read the sentence "You must have a way of making sure microprocessor cannot write to RAM while Phi2 is low" and now I must read that section again!

That dictum also applies to non-65xx I/O hardware. See above for an example of how to generate read/write signals qualified by Ø2.