How about PCM1808 or the AK5358, which are specifically made as audio input ADCs (stereo, 24 bit, up to 96 ksps). But it would depend on the I/O availability.
Sure, that works too. I was thinking of a DC-coupled DAQ-style input which could be used for audio or other purposes as opposed to a dedicated audio unit, but without a specific application in mind, I could go either way.
I was also thinking about using SDRAM instead of SRAM. Instead of 1MB of SRAM, you can get 32MB of SDRAM, using fewer I/O pins, and less money. And as long as you stay in the same page, a random read only takes 3 cycles @ 133MHz, which is still fast enough to support an 8 MHz CPU without wait states. Since you need to offer a windowed view of the RAM anyway, the window could be aligned with the SDRAM page, so you could do random access anywhere in that window. When moving the window, the SDRAM interface would have enough time to activate the new page. Everything outside the SDRAM window, such as executable code, zeropage, stack, and working memory would be mapped to FPGA internal RAM.
What sort of clocking arrangement were you thinking of? We'll need to keep the following in mind:
- VGA clock wants to be 25.175 MHz. VGA memory access can't be delayed, but a FIFO can be used if necessary.
- Would like to run the 65C02/65C816 as fast as possible -- e.g. as close to the limit of 8 MHz as possible.
- SDRAM limit is ~133 MHz.
A system clock frequency of 125.875 MHz would allow you to keep everything in the same clock domain: VGA would be /5, PHI2 would be /16, and the SDRAM can run at the system clock frequency. Otherwise the additional synchronization between clock domains could introduce excessive latency into the system, even though it may allow slightly higher clocking rates.
This doesn't factor in the audio codecs at all either, though since they are low speed devices synchronization won't be an issue if they need their own clock domain.
Did you want to consider making this work both with a 65C02 and a 65C816, or just stick with the 65C02? If the former then it would be worth spending some time to come up with an MMU scheme for the 65C02 that maps onto the 65C816 addressing scheme relatively cleanly. The SDRAM would need to be fast enough to do a random access for the VGA at 25.175 MHz if memory access is to be interleaved with the CPU. At first glance, I don't see any problems there, however.
Would also be nice to have some kind of off-CPU DMA engine available for moving memory around at high speeds. Nice to have for video acceleration, audio, and perhaps even moderately high-speed I/O (e.g. between a microSD card and memory directly rather than going trough the CPU).
In the end, the CPU winds up being like a traffic cop just directing traffic rather than doing any heavy lifting itself.
