We've just posted about the Rockwell 6519, which is on one side strangely incompatible, but on the other hand has what looks like a "Forth instruction" register, with hardware Threaded Next etc opcodes.

https://plus.google.com/108984290462000 ... mULLYcJ1pN

André

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Author of the GeckOS multitasking operating system, the usb65 stack, designer of the Micro-PET and many more 6502 content: http://6502.org/users/andre/

Edit: archive copy of André's link.

Looks like Ted Melton actually had one of these: viewtopic.php?p=2282#p2282

I've written code for the 'C39 (maybe the 'C29, but I think it was the 'C39), which seems to have been somewhat of a follow-on from this CPU. It's used in some Rockwell (or Connexant, or whoever they are now) modem chipsets.

We have the data sheet on this site, at http://archive.6502.org/datasheets/rock ... mputer.pdf

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Let's see how the R65C19 differs from a 6502:
- (indirect,X) becomes (indirect)
- (indirect),Y becomes (indirect),X
- extra instructions - see below - for support of threaded interpreted languages, for arithmetic including multiplication, swap, multiple register push and pull, one-byte subroutine calls (8 available, vectored through ROM)
- 16-bit I register to support threaded interpreted code
- 16-bit W register to support multiply-accumulate
- six levels of IRQ each with their own ROM vector, also (configurable) RAM vector
- JSR and RTS stack the actual return address, and are both 1 cycle faster
- 512 bytes RAM on-chip (spread over half of page 0, all of page 1 and half of page 2)
- the stack is, possibly, somehow segmented into four parts
- optional 16k ROM on-chip
- 15-byte dual-ported buffer to allow the chip to act as a memory-mapped peripheral to a host micro
- various on-chip peripherals and extra I/O ports
- up to 44 GPIOs and/or external memory bus
- four pre-decoded chip select outputs for external memory chips
- comes in 64-pin, 68-pin or 80-pin packages
- stop mode and idle mode
- runs up to 8MHz

Also implemented in CMOS, for better noise immunity, lower power consumption and down-to-DC clocking. And, as we'd expect, the six main bugs of the old NMOS chip are fixed (see page A-5). But, unlike the 'C02, it's not specified as treating undefined opcodes as NOPs. Of course that's generally an issue of no concern -- but still notable if you're interested in the internals of the chip.

-- Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

More food for thought.

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Michael A.

There may be some interest in the opcode map of the R65C19 and how it compares to the R65C02. Pink/Light Red Cells are opcodes which have different meaning than those of the R65C02. Cells with Red Font and a white background are the additions to the 6502 instruction set made by the 65C02. The bit-oriented instructions added by Rockwell are shown in normal black font and a white background in rows 7 and F.

From the map shown in the two attached diagrams, the R65C19 instruction set demonstrates some significant deviations from that of the R65C02/W65C02.

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Michael A.