Breaking 6502 apart

[org]

I still can't fully understand execution order
In top part I have problems with flags input/outputs (still dont know what to do first - input flags from databus, or output current flag values)
In bottom part I have bunch of control lines which can lead to bus conflicts, for example :
If X/SB and Y/SB are become asserted at same time they encounter bus conflict (X and Y are put on SB at same time).

[BigEd]

Ah, yes, outside of normal operation there could be bus conflicts - the undefined opcodes may do this - and you'll most likely get either an AND or an OR of the various writers.

[org]

Quote:

and you'll most likely get either an AND or an OR of the various writers

I will apply "ground wins" rule

BTW, I updated PSD sources too : http://breaknes.com/files/6502/6502.zip [150 MB]

[org]

NMI pad logic

Transistor schematics:

6502.org wrote:

Image no longer available: http://breaknes.com/files/6502/NMI_PAD0.jpg

Logic circuit:

6502.org wrote:

Image no longer available: http://breaknes.com/files/6502/NMI_PAD1.jpg

After removing inverters it turned out to be D flip/flop

6502.org wrote:

Image no longer available: http://breaknes.com/files/6502/NMI_PAD2.jpg

[org]

- Complete decoder labels
- Fixed names for /T0, /T1X and T1 lines

Latest version here : http://breaknes.com/files/6502/6502.jpg

[org]

6502.org wrote:

Image no longer available: https://www.circuitlab.com/circuit/2u6p6k/screenshot/540x405/

[org]

6502.org wrote:

Image no longer available: https://www.circuitlab.com/circuit/t2e9cn/screenshot/540x405/

6502.org wrote:

Image no longer available: https://www.circuitlab.com/circuit/atj32b/screenshot/540x405/

6502.org wrote:

Image no longer available: https://www.circuitlab.com/circuit/5htvew/screenshot/540x405/

This is logic circuits.

[BigEd]

One small point - for a transparent latch, I've seen a symbol used where the clock input is marked with a half- square, instead of a triangle. The triangle means it's an edge-triggered flop.
Cheers
Ed

[zellyn]

The triangle looks like half a square to me... :-p

[BigEd]

Funny!

[org]

Quote:

The triangle means it's an edge-triggered flop.

Thanks, didn't know this detail )

Those D-triggers are implemented as floating gate transistors. And its level-triggered of course. Is there any better way to represent it as logic block ?

[Dr Jefyll]

latch_symbol.png (1.67 KiB) Viewed 1621 times

BigEd wrote:

for a transparent latch, I've seen a symbol used where the clock input is marked with a half- square

Like this, then? Up until now I've just used "LE" to label such an input, but a symbol would be preferable.

Cheers,
Jeff

[BigEd]

That's exactly what I've seen before, thanks Jeff. I couldn't find it though. What I did find was the idea of using a plain input called "E" instead of a triangle-marked input.
Cheers
Ed

[Dr Jefyll]

BigEd wrote:

I couldn't find it though. What I did find was the idea of using a plain input called "E"

Ditto on both points! -- I did a search and found the "E" suggestion but not the symbol. So, I drew one myself. Glad you like it!

[org]

Fixed) I found "custom element" in circuitlab and made "E" input.