A 6502 SoC Project using a Spartan 3 FPGA

ElEctric_EyE · Post by **ElEctric_EyE** » Wed Jan 05, 2011 9:54 pm

Interesting read, a few good links there about the 65832...

history:
http://homepage.mac.com/jorgechamorro/a ... /65xxx.txt
spec sheet:
http://www.obelisk.demon.co.uk/files/W65C832.pdf

But Biged, aren't most of the Xilinx dev boards made by digilent?

BigEd · Post by **BigEd** » Wed Jan 05, 2011 10:05 pm

ElEctric_EyE wrote:

But Biged, aren't most of the Xilinx dev boards made by digilent?

well, there are Xilinx' own offerings, and then there are Xess' products.

$249 http://www.xilinx.com/products/devkits/ ... P601-G.htm

http://www.xess.com/prods/prod035.php

And then, there will be various Altera-based products - I've settled on xilinx but of course others will have the opposite preference.

And then, there are modules like OHO's, which aren't dev boards but allow experimentation with minimal circuit and soldering expertise.

And, just checking at fpga4fun.com, I see there's an outfit called KNJN
http://www.knjn.com/FPGA-FX2.html

And, sparkfun have something: http://www.sparkfun.com/products/8458

So, amongst other things, getting an idea of which boards people have used and would recommend might be good!

Cheers
Ed

Edit: added quote to make this self-contained

Edit: see this new specific thread about dev boards

ElEctric_EyE · Post by **ElEctric_EyE** » Wed Jan 05, 2011 10:12 pm

I, for one, think that would definately be useful. I forgot about Xess...

I would be posting the other cores I plan on implementing, but opencores.org is down... So...

I'm gonna ramble on here, because I've been reading that previous thread about the 65032/832. Probably the reason it never got off the ground was anticipated lack of software support.

The 6502 has loads of useful software, be it assemblers, etc. When I made the jump to the 65816 recently, I become a little more restricted in taking advantage of the chip. Then the 65032/832? So what if you have a piece of silicon. Unfortunately, you can't develop with it unless there is software to support it. I think there is a shortage of M. Kowalski types around...

I guess what I'm saying is: It is nice to have backward hardware compatibility, but I shouldn't have to pay for a $500 software dev kit. I don't want a $500 IC either... Why not make the IC cost more and make the dev software free? I would pay >$50 <$100 per '816, if I had a good software product to develop it with...

Mass production doesn't start instantly... It all starts with the individual tinkerer. I think someone has lost sight of this in their accounting dep't formulas.

Look at the success of Xilinx FPGA's/CPLD's. Their software is readily available, and easy to use to develop their IC's, even without the need for evaluation boards...

Arlet · Post by **Arlet** » Thu Jan 06, 2011 7:41 am

ElEctric_EyE wrote:

I have the same desire, but wish to make custom boards in the end, and save money by not purchasing an eval board.

Which version of Spartan 3 is on your eval board?
What kind of eval board do you have?

I have this board, which I bought several years ago from Xilinx, and isn't in production anymore: http://www.xilinx.com/products/devkits/ ... -UNI-G.htm

It's got a X3S200 FPGA, 8-color VGA interface, PS2, RS232, 7-seg displays, 8 leds, switches, and 1MB worth of SRAM. It came with a parallel-JTAG cable, software, and documentation. I think it was $99 for the kit, which is a pretty good deal. It probably would have cost me more to buy all the components separately. The size of the FPGA is plenty for hobby projects, especially if you write most of the code yourself it will be hard to fill up even the small device. I don't think I ever got it more than 1/3rd full for a project that included a dual USB interface, 16 bit CPU and SDRAM controller.

It looks like digilent still sells this board, or at least something very similar for $109: http://www.digilentinc.com/Products/Det ... od=S3BOARD but they've dropped the free programming cable.

ElEctric_EyE · Post by **ElEctric_EyE** » Thu Jan 06, 2011 10:54 pm

I see my usage of an XC3S400 is serious overkill. I pursued it early on, I believe it was almost a year ago, only because it is the largest FPGA Xilinx sells in a solder friendly QFP and I wasn't sure way back then what would fit into it... I think I'll check Avnet's supplies of various Spartan 3 flavors.

OpenCores.org is back up so these are the cores I am going to try to fit:

I2C
PS2
SD Card

They all have wishbone interfaces.

Edit: Earlier I mistakenly wrote the I2C core did not have a wishbone interface.

ElEctric_EyE · Post by **ElEctric_EyE** » Thu Jan 06, 2011 11:50 pm

I did find and order 2 more versions of the Spartan 3. The smallest XC3S50 in 100-pin QFP for ~$8US, and the XC3S200 in 144-pin QFP for ~$13US.

Then it got me thinking what is the next family up that is still available in a solderable package (from a hobbyists' POV). Call me mad, but since Santa was good to me, I had to order 1 more IC. The Virtex FPGA in 240-pin QFP @~$127US to experiment with. That is alot of money for 1 IC!

As I said, I think I may be insane, but what if one day, after mastering the art of Verilog/HDL it's not available, like so many of the TTL IC's nowadays... I had to get one. I'm sure it is very capable... My precious!

Now I have some good reads tonight on this Virtex data sheet...
_____________________________________________________________

Been reading the Virtex product spec's. From 2001... Wiki says it's old tech not recommended for new designs. Oh well... One item that did catch my EyE was about 1/2 way down on the previous link: "- Internal 3-state bussing". I'll be experimenting with this feature. It sounds like one could have tri-states internal to the IC, not just at the top-level.

Arlet · Post by **Arlet** » Fri Jan 07, 2011 6:47 am

Disadvantage of internal 3-state buses is that a design mistake can cause an internal short.

ETA: By the way, even when the FPGA doesn't support internal 3-state buses, you can still use the same code in your HDL description, so it doesn't really matter whether the hardware supports it. On devices without internal buses, the synthesizer will just convert your code to an equivalent version with MUXes.

Another trick I've used for internal buses, say for instance the DI (data in) bus from all kinds of peripherals to the CPU is a 2-state bus, which is equivalent to a 3-state bus, but instead of 'Z' you use '0'. At the end of the bus, you can then simply OR all the signals together. A single LUT can perform a 4-input OR, but it can only do a 2-input MUX (4 LUTs are needed for a 4 input MUX). This DI path is very critical, because it connects to what is already the longest path inside the 6502 (the ALU combinatorial block), so any extra logic you put on the outside of the DI bus has an immediate impact on overall speed.

Konrad_B · Post by **Konrad_B** » Fri Jan 07, 2011 10:54 am

Arlet wrote:

I have this board, which I bought several years ago from Xilinx, and isn't in production anymore: http://www.xilinx.com/products/devkits/ ... -UNI-G.htm
[...]
I think it was $99 for the kit, which is a pretty good deal.

Yes, it was $99 - which makes it (probably) the cheapest 256k x 32 logic analyzer, with a little help from the sump.org (http://www.sump.org/projects/analyzer/)

BigEd · Post by **BigEd** » Fri Jan 07, 2011 11:09 am

Good point this - because the front-page diagram suggests only a 16-bit memory interface. The PDF confirms that there are 2x16bit chips configured to give a 32-bit wide data interface. (NEXSYS2 only has 16-bit wide databus to on-board memory).

Along with USB-powered, and USB-programmable, (this board is neither) these are for me important characteristics. Also I/O count and 5v compatibility. And price.

The PDF:

6502.org wrote:

Image no longer available: http://img341.imageshack.us/img341/3807/xilinxspartan3boarddiag.th.jpg

The webpage:

6502.org wrote:

Image no longer available: http://img257.imageshack.us/img257/3807/xilinxspartan3boarddiag.th.jpg

Arlet · Post by **Arlet** » Fri Jan 07, 2011 11:15 am

Konrad_B wrote:

Yes, it was $99 - which makes it (probably) the cheapest 256k x 32 logic analyzer, with a little help from the sump.org (http://www.sump.org/projects/analyzer/)

Looks like they keep WE# asserted while changing address lines on the SRAM. Seems out of spec, but I suppose that any glitches are short enough that it'll work. Never dared doing this myself...

Arlet · Post by **Arlet** » Fri Jan 07, 2011 11:16 am

BigEd wrote:

Good point this - because the front-page diagram suggests only a 16-bit memory interface.

Actually your first image shows the two SRAMs as separate devices.

BigEd · Post by **BigEd** » Fri Jan 07, 2011 11:18 am

Indeed - the first image is from the PDF. (Edit: I've annotated that post now!)

Arlet · Post by **Arlet** » Fri Jan 07, 2011 11:28 am

Ok, got it.

The RAM on the NEXYS2 offers a high speed burst mode, so you can still get a very good throughput without having to rely on out-of-spec tricks. It's also bigger. There will be some extra cost for the interfacing, though.

BigEd · Post by **BigEd** » Fri Jan 07, 2011 11:39 am

Thanks, that's worth knowing.

(I've added a couple of words to my post with pictures, to help clarify.)

ElEctric_EyE · Post by **ElEctric_EyE** » Sat Jan 08, 2011 12:32 am

Arlet wrote:

...ETA: By the way, even when the FPGA doesn't support internal 3-state buses, you can still use the same code in your HDL description, so it doesn't really matter whether the hardware supports it. On devices without internal buses, the synthesizer will just convert your code to an equivalent version with MUXes...

The Spartan 2 was the first FPGA I grappled with after migrating from the XC9572 CPLD, schematic-only design entry. I was at the point of using 2 CPLD's and decided to tackle Xilinx FPGA's. However, ISE would not let me get away with what I described here... So it sounds very similar to what you have described. Others here seem to be having problems with internal bi-directional busses in HDL/Verilog...

I was just not aware that any Xilinx FPGA's would allow internal tri-states like their current CPLD's. I guess that's why the Virtex is a legacy device only able to be used with ISE10.1. Just a curiosity, I don't intend to focus on it now.

What I would really like to know about, is your USB interface. Did you write your own, or use another core? Is it register based? Easily interfaced to the 6502?
I chose an SD card interface for non volatile mass storage because it looks easier... I am interested in pluggable/unpluggable non-volatile mass storage, because I would like to lose my old EEPROM burner...

BTW, what is ETA?