It would have a base board with power supply, clock oscillator, 65C02, 32K SRAM, 32K EEPROM that could be written in-system, the DEC-1, and a dedicated serial terminal port. This board could run all by itself.
I would add an I/O connector that contained the data bus, A0-A3, the 4 IO Selects from DEC-1, PHI2, RW, IRQ, RESET, and power.
A daughter board would then be stacked on top of this connector with a matching female socket and standoffs. This board would have a staggered I/O connector facing up that would allow another board to be stacked on top.
The IO selects would be shifted between the bottom and top connector ( 2->1, 3->2, 4->3, +5v->4), similar to the 65SIB Slave selects, to allow for each board to be automatically addressed, based on its position in the stack.
This way, each builder could add his own suite of IO devices.
There could be modules with: 65C22, 65SPI, Mass storage, Video, sound , GP IO, etc. Each board would have 16 bytes of address space. That value could be increased to 32 or 64 bytes easily - at the expense of having more address lines on the IO connector. You can even have two or more of the same type module.
By limiting the stack to 4, there would be some control over the bus loading to keep performance moderately high. Again, if the consensus is to allow for more, that could be accommodated at the expense of increased bus loading.
Having the daughter boards staggered would allow for IO connectors to be easily accessed.
It would look something like this:

A 65816 version of the base board could also be made and users could even create their own custom daughter boards using perfboard, as the spacing would be standardized on 0.1" centers.
All comments welcome.
Daryl
